Yutaka Ishibashi

Measurement of contact resistance distribution using a 4k-contacts array

A new test structure suitable for measuring a contact resistance distribution has been developed. It includes the following two components: (1) a 256 row, 16 column (=4096) four-terminal cross-contact array; and (2) peripheral circuits, which consist of an eight-stage CMOS binary counter and 256 bit CMOS decoders. It was found that contact resistance can be fitted by a Gaussian distribution more than three standard deviations of the mean value. The relationships between the contact size and the standard deviation of the contact resistance has been discussed for two types of contacts: Al/TiN/TiSi/sub 2/-n+Si and WSi/sub 2//poly-n+Si. This test structure can simultaneously measure the series resistance of a two-terminal contact chain and the individual contact resistance. Comparing these results, it was found that the increase of the series resistance of the contact chain is due to the appearance of the contact that is outside of the Gaussian distribution.

A High-performance Multi-level NAND Flash Memory with 43nm-node Floating-gate Technology

Multi-level programming is demonstrated with 43 nm-node NAND floating-gate megabit cells for the first time, by thinning an inter-gate dielectric film to less than 13 nm. 43 nm-node cobalt-silicide control-gate and copper bit-line technologies are developed to achieve low resistances of the word lines and bit lines.

NAND-structured cell technologies for low cost 256 Mb DRAMs

NAND-structured cell technologies for low cost DRAMs have been demonstrated. Two kinds of cell structure have been developed, a stacked type NAND-structured cell for 256 Mb and a trench type cell for 256 Mb and beyond. In order to maximize plane view area of the storage node of the NAND-structured STC, a transparent phase shift mask has been used. Sufficient storage capacitance can be obtained with one lithography and one RIE process. The NAND-structured trench cell has advantage for miniaturization. In this cell configuration, the deep trench for the capacitor also used for the trench isolation between neighboring cells. The junction leakage current from the storage node can be reduced by using a p/sup +/ substrate.<<ETX>>

Reliability improvement in planar MONOS cell for 20nm-node multi-level NAND Flash memory and beyond

20nm-node planar MONOS cell which has improved reliability is developed. Extremely wide program/erase Vth window and good retention characteristics after cycling stress are obtained by buried charge cell structure. Moreover, Vth shift by interference between adjacent cells has smaller dependence on the cell-cell space than Vth window improvement when the half pitch is constant. These results show that the buried charge planar MONOS cell is suitable for Flash memory with 20nm-node and beyond.

Liner-supported cylinder (LSC) technology to realize Ru/Ta/sub 2/O/sub 5//Ru capacitor for future DRAMs

The concept of liner-supported cylinder (LSC) technology to realize robust formation of cylindrical electrodes with Ru, which has advantages to bring out the best of Ta/sub 2/O/sub 5/ performance, is described. With experimental results including DRAM functionality, we show that LSC-Ta/sub 2/O/sub 5/ capacitor is a promising candidate to realize 0.10 /spl mu/m DRAMs and beyond.

All perovskite capacitor (APEC) technology for (Ba,Sr)TiO/sub 3/ capacitor scaling toward 0.10 /spl mu/m stacked DRAMs

All perovskite Capacitor (APEC) technology is proposed to achieve (Ba,Sr)TiO/sub 3/ (BST) capacitor scaling toward 0.10 /spl mu/m DRAM generation. A conductive perovskite-oxide (polycrystalline SrRuO/sub 3/ (SRO)) electrode is introduced as a bottom and a top electrode of BST capacitor. Advantages of APEC technology are low leakage current and less damage to hydrogen-annealing. A new BST-CVD tool with a good film uniformity is also developed to realize a BST film thickness decrease. Both APEC and the new BST-CVD tool are found to be a promising technology for future BST capacitors scaling.

Low temperature (Ba,Sr)TiO/sub 3/ capacitor process integration (LTB) technology for gigabit scaled DRAMs

Low temperature (600/spl deg/C) (Ba,Sr)TiO/sub 3/ (BST) capacitor process integration (LTB) based on a SrRuO/sub 3/ (SRO) electrode is proposed to achieve gigabit scaled and embedded DRAMs. The BST crystallization temperature is successfully reduced by SRO, which has the same perovskite structure as the BST film. Chemical Mechanical Polishing (CMP) and O/sub 3/ water etching are developed for storage node (SN) electrode and plate (PL) electrode patterning. A new low temperature post anneal method is also proposed in order to reduce oxygen vacancies at the top electrode-BST interface.