Masami Aoki

An experimental DRAM with a NAND-structured cell

An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The NAND-structured cell has four memory cells connected in series, which reduces the area of isolation between the adjacent cells and also reduces the bit-line contact area. The cell area per bit measures 0.962 mu m/sup 2/, using 0.4- mu m CMOS technology, which is 63% in comparison with the conventional cell. In order to reduce the die size, time division multiplex sense-amplifier (TMS) architecture, in which a sense amplifier is shared by four bit lines, has been newly introduced. The chip area is 464 mm/sup 2/, which is 68% compared with the DRAM using the current cell structure. The data can be accessed by a fast-block-access mode up to 512 bytes as well as a random access mode. Typical 112-ns access time of the first data in a block and 30-ns serial cycle time are achieved. >

Measurement of contact resistance distribution using a 4k-contacts array

A new test structure suitable for measuring a contact resistance distribution has been developed. It includes the following two components: (1) a 256 row, 16 column (=4096) four-terminal cross-contact array; and (2) peripheral circuits, which consist of an eight-stage CMOS binary counter and 256 bit CMOS decoders. It was found that contact resistance can be fitted by a Gaussian distribution more than three standard deviations of the mean value. The relationships between the contact size and the standard deviation of the contact resistance has been discussed for two types of contacts: Al/TiN/TiSi/sub 2/-n+Si and WSi/sub 2//poly-n+Si. This test structure can simultaneously measure the series resistance of a two-terminal contact chain and the individual contact resistance. Comparing these results, it was found that the increase of the series resistance of the contact chain is due to the appearance of the contact that is outside of the Gaussian distribution.

NAND-structured cell technologies for low cost 256 Mb DRAMs

NAND-structured cell technologies for low cost DRAMs have been demonstrated. Two kinds of cell structure have been developed, a stacked type NAND-structured cell for 256 Mb and a trench type cell for 256 Mb and beyond. In order to maximize plane view area of the storage node of the NAND-structured STC, a transparent phase shift mask has been used. Sufficient storage capacitance can be obtained with one lithography and one RIE process. The NAND-structured trench cell has advantage for miniaturization. In this cell configuration, the deep trench for the capacitor also used for the trench isolation between neighboring cells. The junction leakage current from the storage node can be reduced by using a p/sup +/ substrate.<<ETX>>

Determination of the diffusion coefficients of NiCl2, ZnCl2, and CdCl2 in aqueous solution

The diffusion coefficients of NiCl2, ZnCl2, and CdCl2 in the aqueous solution systems of MC12 and MC12-HC1 were measured at 298 K using a diaphragm-cell method. The data are listed as a function of molar concentrations of MC12 at the HC1 concentrations of 0, 0.1, 0.5, 1.0, and 2.0 mol dm-3. It was found that the concentration dependencies of the diffusion coefficients for these metal chlorides in single-electrolyte solutions differed from each other. This could be explained in terms of changes in the mean activity coefficients of chloride and in the viscosities of those solutions. The diffusion coefficient of metal chloride in MC12-HC1 solution was greatly affected by the HC1 concentration; however, the behavior of the diffusion coefficients varied, depending on the kind of chloride involved. In NiCl2-HCl solutions, an increase in HC1 con-centration caused a decrease in the diffusion coefficient value, while in ZnCl2-HCl solutions, the addition of 2 mol dm-3 HC1 caused an increase in the diffusion coefficient of ZnCl2. These phenomena are quite different from those of the sulfate systems reported in our previous work. It was also demonstrated that the concentration dependency of the diffusion coefficients of MC12 in aqueous MC12-HC1 solutions could be attributed to the diffusion potential as well as the changes in the mean activity coefficient and viscosity.

Triple density DRAM cell with Si selective growth channel and NAND-structure

We propose a novel trench capacitor cell suitable for shrinkage, named triple density cell (TD-cell). The TD-cell has a planar transistor which overhangs a storage trench capacitor, and Si selective epitaxial growth (SEG) is used for channel formation. The cell size reduces to ultimately 33% for the conventional folded-bit-line arrangement, by combining this stacked configuration and NAND-structured cell arrangement. We also verified and analyzed threshold and sub-threshold transport for transistors made on SEG Si layer.<<ETX>>

0.29-/spl mu/m/sup 2/ trench cell technologies for 1G-bit DRAMs with open/folded-bit-line layout and selective growth technique

We present substrate-plate-trench cell technologies for 1G-bit DRAMs. With an open/folded-bit-line layout, the smallest cell area of 0.29 /spl mu/m/sup 2/ was realized for a 0.20 /spl mu/m design rule. A pause time of 4.2 s at 85/spl deg/C and an activation energy of 0.70 eV were achieved for a 0.25-/spl mu/m/spl Phi//spl times/4-/spl mu/m trench capacitor. A new Si selective epitaxial growth (SEG) technique was developed to reduce connection formation between the capacitor and transistor to one fabrication step, and also reduce a distance between the trench and gate. The gate capacitors on the SEG showed a breakdown electric field over 11 MV/cm even when the distance was less than 0.1 /spl mu/m.