Yutaka Okada

An advanced bipolar-MOS-I 2 L technology with a thin epitaxial layer for analog-digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I2L) and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-µm design rule. Thin epitaxial layer (\leq 2 \microm) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n+buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.

A new "SICOS" Schottky device

A new Schottky barrier diode (SBD) structure with a very small self-aligned guard ring has been proposed. This device is compatible with the SICOS (SIdewall base COntact Structure) process [1] [2]. The key technology is lateral impurity diffusion from doped poly-silicon, which makes guard ring size very small and improves the clamping effectiveness of SBDs. Very high speed Schottky TTL circuits using proposed devices are demonstrated which achieve a gate delay time of 330 ps/gate (fan in=3) with 2.3 mW/gate power dissipation, making them very attractive for use in high performance bipolar VLSIs.