Yuuki Ogata

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline chip-to-module or chip-to-chip communications [1-3]. To achieve better power efficiency than that of existing 25Gb/s/signal designs, a high-speed yet energy-efficient front-end is needed in both the transmitter and receiver. A receiver front-end with baud-rate architecture [1] has been successfully operated at 56Gb/s, but additional components such as eye-monitoring comparators, phase detectors, and clock recovery circuitry as well as a power-efficient transmitter are needed to build a complete transceiver.

A Single-Chip, 10-Gigabit Ethernet Switch LSI for Energy-Efficient Blade Servers

The use of virtualization technology has been increasing in the IT industry to consolidate servers and reduce power consumption significantly. As a virtualization platform, a large-scale blade server is suitable because it can hold a dozen blades in a chassis with well managed configuration, enabling easy provisioning. To realize an energy-efficient blade server, the network component must deliver both high performance and reduced power consumption. We developed the fifth generation single-chip 10GbE switch LSI that supports 26 10GbE ports with built-in 10 Gb/s serial back plane interfaces. Using this highly integrated switch LSI, we also developed a single-wide 10GbE switch blade for the blade server. The switch blade delivers 100 percent more performance per watt than other 10GbE switch blades in the industry. This paper describes the features of the switch LSI, the high-speed IO circuit of its built-in interfaces and 10GbE switch blade.

32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE

We demonstrate that a 32Gb/s transmitter with a 4-way interleaved configuration is feasible in 28nm CMOS. A bit in the data stream contributes to a 2UI-wide pulse in the output signal, eliminating the need for 2-to-1 MUXs and enabling the use of quarter-rate clocking. A 4-tap 1UI-spacing FIR filter is implemented in the transmitter to compensate for the signal loss in the signal transmission media. The output signal is compatible with conventional NRZ receivers with a DFE.

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution

A 36-Gbps transceiver with a continuous-time linear equalizer and a 1-tap DFE in 20-nm CMOS is demonstrated. The transceiver uses a quarter-rate (i.e., 9-GHz) differential-clock distribution to reduce the clock-delivery power. Multi-phase half-rate clock signals that drive the transceiver front-ends are generated by a delay-locked loop and frequency doublers that systematically reduce the impact of skew and jitter. The transceiver occupies 0.55 mm2 and consumes 609.9 mW of power from a 0.9-V supply.

6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance

As we move to higher data rates, the performance of clock and data recovery (CDR) circuits becomes increasingly important in maintaining low bit error rates (BER) in wireline links. Digital CDRs are popular in part for their robustness, but their use of bang-bang phase detectors (BB-PD) makes their performance sensitive to changes in jitter caused by PVT variations, crosstalk or power supply noise. This is because the gain of a BB-PD depends on the CDR input jitter, causing the loop gain of the CDR to change if the jitter magnitude or spectrum varies. This problem is illustrated in Fig. 6.7.1 where small jitter leads to excessive loop gain and hence to an underdamped behaviour in the CDR jitter tolerance (JTOL), while large jitter leads to insufficient loop gain and hence to low overall JTOL. To prevent this, we propose a CDR with an adaptive loop gain, KG, as shown in Fig. 6.7.1.

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

28.3 Gb/s transceiver with 35 dB channel loss equalization is presented. The transmitter deploys 3-tap feed forward equalizer (FFE). The driver employs the hybrid architecture of low voltage differential signaling (LVDS) and source-series-terminated (SST) driver which enables the low power consumption and output signal amplitude fine tune. The receiver comprised with continuous time linear equalizer (CTLE) and 2-tap loop unrolled decision feedback equalizer (DFE). It saves the power consumption by not applying DFE at the eye edge, and increases the eye margin with adaptive sampling clock phase adjustment capability. The transceiver is composed of one PLL and four lanes, occupies 1.67 mm2 and consumes 829 mW (7.3 pJ/bit).