Yuusuke Tanaka

Extreme Ultraviolet Lithography Using Small-Field Exposure Tool: Current Status

The small-field exposure tool (SFET) for extreme ultraviolet (EUV) lithography was manufactured by Canon and EUVA and installed in Selete. It is being used for developing mask, resist, and tool technologies. In this paper, we review the current status of SFET development and present some initial results on lithographic performance and tool stability.

Flare evaluation for 32-nm half pitch using SFET

Flare degrades critical-dimension (CD) control in EUVL, a promising technology for the 32-nm half-pitch node. To deal with flare, high-quality projection optics in the exposure tool and flare variation compensation (FVC) technology with proper mask resizing are needed. Selete has installed a small-field exposure tool (SFET) with the goal of assessing resist performance. Due to the high-quality optics, the SFET allowed us to determine the required flare specification to be 6.1% or 6.6%, as calculated from the residual part of the low- or middle-frequency region, respectively. The flare level was confirmed through experimental results and from calculations using the power spectral density (PSD) obtained from the mirror roughness by the disappearing-resist method. The lithographic performance was evaluated using 32-nm-halfpitch patterns in a new resist. The resist characteristics can be explained by modeling blur as a Gaussian function with a σ of 8.8 nm and using a very accurate CD variation (< ~6 nm) obtained by taking into account the influences of mask CD error and flare on evaluation patterns. Since FVC is needed to obtain flare characteristics that do not degrade the CD, we used the double-exposure method to eliminate the influence of errors, including nonuniform dose distribution and CD mask error. Regardless of whether there was an open area or not, there was no difference in CD as a function of distance up to a distance of 20 µm. In addition, CD degradation was observed at distances not far (< 5 µm) from the open area. In a 60-nm neighborhood of the open area, an 8-nm variation in CD appeared up to the distance at which the CD leveled off. When the influences of resist blur and flare on patterns was taken into account in the calculation, it was found that aerial simulations based on a rigorous 3D model of a mask structure matched the experimental results. These results yield the appropriate mask resizing and the range in which flare has an influence, which is needed for FVC. This research was supported in part by NEDO.

Light-shield border impact on the printability of extreme-ultraviolet mask

When a thinner absorber mask is applied to extreme ultraviolet (EUV) lithography for chip production, it becomes essential to a introduce light-shield border in order to suppress the leakage of EUV light from the adjacent exposure shots. In this paper, we evaluate the leakage of both EUV and out-of-band from light-shield border and clarify the dependence of lithographic performance on light-shield border structure using a small field exposure tool with/without spectral purify filter (SPF). Then we evaluate the lithographic performance of a thin absorber EUV mask with light-shield border of the etched multilayer type and demonstrate the merit of its structure using a full-field scanner operating under the currently employed condition of EUV source in which SPF is not installed.

Recent progress of EUV full-field exposure tool in Selete

The Selete full-field EUV exposure tool, the EUV1, was manufactured by Nikon and is being set up at Selete. Its lithographic performance was evaluated in exposure experiments with a static slit using line-&-space (L&S) patterns, Selete Standard Resist 03 (SSR3), an NA of 0.25, and conventional illumination (σ = 0.8). The results showed that 25- nm L&S patterns were resolved. Dynamic exposure experiments showed the resolution to be 45 nm across the exposure field and the CD uniformity across a shot to be 3 nm, also 26-nm L&S patterns were resolved. Overlay performance of the EUV1 was showed as processed wafer mark alignment, the repeatability was under 1nm. Overlay accuracy using EGA (Enhanced Global Alignment) was below 4nm at the 3-sigma after liner correction. These results were good enough for an alpha-level lithography tool and test site verification.

Effects of aberration and flare on lithographic performance of SFET

The effects of aberration and flare on the lithographic performance of the EUV small-field exposure tool (SFET) were evaluated. Simulation results indicated that the effect of aberration on the image contrast of line-and-space (L&S) patterns should be small. In exposure experiments, 26-45-nm L&S patterns were successfully fabricated under annular illumination (σ=0.3/0.7). A key factor limiting resolution should be resist performance. Simulation results also indicated that the astigmatic aberration could produce a focal shift of about 60 nm between horizontal and vertical L&S patterns. The experimentally obtained focus shift agreed well with the simulation results. Dense 32-45-nm contact-hole (C/H) patterns were also successfully fabricated under annular illumination (σ=0.3/0.5). Due to astigmatic aberration, the C/H patterns were deformed at defocused positions, but they were almost circular at the best focus position. The flare of the projection optics measured by the Kirk method was 11% over a flare range of 1-100 μm. The effects of the 11% flare were evaluated using dark- and bright-field 32-nm L&S patterns. It was found that the top loss and line-width roughness (LWR) of the resist were larger for bright-field than for dark-field patterns. To reduce the impact of flare, we need EUV resists that are more robust with regard to flare. A comparison of the measured point spread function (PSF) of the flare and the calculated PSF revealed good agreement for long-range flare but some difference for short-range flare.

Magnification correction by changing wafer temperature in proximity x-ray lithography

Magnification errors arising from wafer processing cause significant overlay errors in lithography. We have devised a new, simple method that involves changing the wafer temperature to correct magnification errors on an x-ray stepper. A wafer is first heated in the wafer orientation unit, and then it is allowed to cool as it is transferred to the wafer stage due to the temperature difference between the wafer and the air in the chamber. For a given cooling time, the reproducibility of the wafer temperature is less than 0.3 °C; and the maximum available temperature change is 1.5 °C. The key point is that the placement of patterns on a wafer immediately after the chucking remains fixed regardless of further changes in the wafer temperature, provided that the force holding the wafer to the stage is strong enough. The maximum magnification error that can be corrected by this method is about 4 ppm. This is determined by the maximum available temperature change (1.5 °C) and the coefficient of linear expansion f...

Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects

Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication. This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35 nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal- 2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm. The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.

Evaluation of dry etching and defect repair of EUVL mask absorber layer

EUVL mask process of absorber layer, buffer layer dry etching and defect repair were evaluated. TaGeN and Cr were selected for absorber layer and buffer layer, respectively. These absorber layer and buffer layer were coated on 6025 Qz substrate. Two dry etching processes were evaluated for absorber layer etching. One is CF4 plasma process and the other is Cl2 plasma process. Etch bias uniformity, selectivity, cross section profile and resist damage were evaluated for each process. Disadvantage of CF4 plasma process is low resist selectivity and Cl2 plasma process is low Cr selectivity. CF4 plasma process caused small absorber layer damage on isolate line and Cl2 plasma process caused Cr buffer layer damage. To minimize these damages overetch time was evaluated. Buffer layer process was also evaluated. Buffer layer process causes capping layer damage. Therefore, etching time was optimized. FIB-GAE and AFM machining were applied for absorber layer repair test. XeF2 gas was used for FIB-GAE. Good selectivity between absorber layer and buffer layer was obtained using XeF2 gas. However, XeF2 gas causes side etching of TaGeN layer. AFM machining repair technique was demonstrated for TaGeN layer repair.

130 nm and 150 nm line-and-space critical-dimension control evaluation using XS-1 x-ray stepper

Critical-dimension (CD) control for 130 and 150 nm line-and-space (L/S) patterns printed with the XS-1 x-ray stepper was evaluated using two kinds of resists: SAL606 and TDUR-N908. The largest factor in the CD variation was the nonuniformity of the x-ray dose, which was ±4.4% in a 20 mm×20 mm field. In replicated resist patterns, the CD variation due to mask-CD variation dropped to less than half the mask-CD variation because of Fresnel diffraction. For 130 nm L/S patterns, the CD variation for an 8-in.-diam wafer was 7.9 nm (3σ) for SAL606, and 12.0 nm (3σ) for TDUR-N908. For 150 nm L/S patterns, the values were 10.5 nm (3σ) and 14.6 nm (3σ), respectively. Although the major factors causing CD variation are dose nonuniformity and mask-CD variation, different resist materials reflect the effects of these factors to different degrees. The CD variation of 150 nm L/S patterns among seven wafers exposed on the same day was ±2.8 nm for SAL606 and ±3.7 nm for TDUR-N908, which is most likely due to fluctuations ...

Resolution capability of SFET with slit and dipole illumination

A high-resolution EUV exposure tool is needed to facilitate the development of EUV resists and masks. Since the EUV small-field exposure tool (SFET) has a high numerical aperture (NA = 0.3), low aberration & flare, and excellent stage stability, it should be able to resolve fine L/S patterns for the half-pitch 22-nm & 16-nm nodes. In this study, we evaluated the resolution capability of the SFET and obtained 22-nm L/S patterns with x-slit illumination and clear modulation of 16-nm L/S patterns with x-dipole illumination. The resolution limit of the SFET seems to be about 15 nm. The main cause of pattern degradation in 16-nm L/S is probably resist blur. To obtain good shapes for this pattern size, the resist blur of less than 3.5 nm (σ) is required. The use of y-slit illumination was found to reduce the linewidth roughness (LWR) of resist patterns. Further reduction of the LWR requires a higher image contrast and a smaller flare. Due to the central obscuration, the image contrast of the SFET is sensitive to the change of pupil fill. The degradation in the collector & DMT should be reduced to ensure stable aerial images. This work was supported in part by NEDO.