Yuzo Takamatsu

On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits

Diagnosing multiple stuck-at faults in combinational circuits using singleand multiple-fault simulation is proposed. The proposed method adds (removes) faults from a set of suspected faults depending on the result of multiple-fault simulation at a primary output agreeing (disagreeing) with the observed value. However, the faults that are added or removed from the set of suspected faults are determined using single-fault simulation. Diagnosis is carried out by repeated addition and removal of faults. The effectiveness of the diagnosis method is evaluated by experiments conducted on benchmark circuits and it is found to be substantially superior compared to the previous known solutions. The method proposed in this paper can be used as a powerful tool at the preprocessing stage of diagnosis in an electron-beam tester environment.

Diagnostic test generation for transition faults using a stuck-at ATPG tool

This paper presents a diagnostic test generation method for transition faults. As two consecutive vectors application mechanism, launch on capture test is considered. The proposed algorithm generates test vectors for given fault pairs using a stuck-at ATPG tool so that they are distinguished. If a given fault pair is indistinguishable, it is identified. Therefore the proposed algorithm provides a complete test generation regarding the distinguishability. The conditions for distinguishing a fault pair are carefully considered, and they are transformed into the conditions of the detection of a stuck-at fault, and some additional logic are inserted in a CUT for the test generation. Experimental results show that the proposed method can generate test vectors for distinguishing the fault pairs that are not distinguished by commercial tools, and also identify all the indistinguishable fault pairs.

Multiple fault diagnosis by sensitizing input pairs

Interpolating subdivision schemes let users adjust coordinates of a 3D objects initial vertices, generate new vertices, and replace the original mesh with more and smaller polygons to make the objects surface smoother. Two new schemes for triangular meshes extend and combine existing schemes to improve the process and its results.

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines

Under the modern manufacturing technologies, the open defect is one of the significant issues to maintain the reliability of DSM circuits. However, the modeling and techniques for test and diagnosis for open faults have not been established yet. In this paper, we give an important clue for modeling an open fault with considering the affects of adjacent lines. Firstly, we use computer simulations to analyze the defective behaviors of a line with the open defect. From the simulation results, we propose a new open fault model that is excited depending on the logic values at the adjacent lines assigned by a test. Next, we propose a diagnosis method that uses the pass/fail information to deduce the candidate open fault. Finally, experimental results show that the proposed method is able to diagnose the open faults with good resolution. It takes about 6 minutes to diagnose the open fault on the large circuit (2M gates).

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits

Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored. The compaction of diagnostic test vectors must take care of all fault pairs that need to be distinguished by a given test vector set. Clearly, the number of fault pairs is much larger than the number of faults thus making this problem very difficult and challenging. The key contributions of this paper are: 1) to use techniques for reducing the size of fault pairs to be considered at a time, 2) to use novel variants of the fault distinguishing table method for combinational circuits and reverse order restoration method for sequential circuits, and 3) to introduce heuristics to manage the space complexity of considering all fault pairs for large circuits. Finally, the experimental results for ISCAS benchmark circuits are presented to demonstrate the effectiveness of the proposed methods

A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations

In this paper, we propose a new method that uses single and multiple fault simulations to diagnose multiple stuck-at faults in combinational circuits. On the assumption that all suspected faults are equally likely in the faulty circuit, multiple fault simulations are performed. Depending on whether or not a multiple fault simulation results in primary output values that agree with the observed values, faults are added to or removed from a set of suspected faults. Faults which are to be added to or removed from the set of suspected faults are determined using single fault simulation. Diagnosis is effected by repeated additions and removals of faults. The effectiveness of the method of diagnosis has been evaluated by experiments conducted on benchmark circuits. The proposed method achieves a small number of suspected faults by simple processing. Thus, the method will be useful as a preprocessing stage of diagnosis using the electron-beam tester.

Timing-Aware Diagnosis for Small Delay Defects

As semiconductor technologies progress, testing of small delay defects are becoming more important for SoCs. However, fault diagnosis of small delay defects has not been developed. We propose a novel timing-aware method for diagnosing small delay defects with a small computation cost using gate delay fault simulation with the minimum detectable delay, as introduced in the statistical delay quality model. The experimental results show that the proposed method is capable of identifying fault locations for small delay defects with a small computation cost.

Diagnosis of Transistor Shorts in Logic Test Environment

For deep-sub micron technology based LSIs, conventional stuck-at fault model is no longer sufficient for fault test and diagnosis. This paper presents a method of fault diagnosis for transistor shorts in combinational and full-scan circuits under logic test environment. Description of a short requires a very large number of physical parameters, and hence it is difficult, if not impossible, to describe precisely the behavior of transistor shorts. Therefore, two types of transistor short models were defined and algorithms to address the diagnostic problem were developed. The novelty of the algorithms is that they use conventional stuck-at fault simulation methodologies to diagnose transistor level shorts. Experiments were conducted on benchmark circuits to demonstrate the effectiveness of the method

Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing

In this paper, we improve the previous method by enhancing a set of diagnostic tests and using an EB testing method. We first enhance the previous set of diagnostic tests to one of diagnostic tests consisting of the four sets, TP-1, TP-2, TP-3 and TP-4. We next present two diagnostic methods by using the enhanced diagnostic tests and an electron-beam tester (EB-tester). Experimental results show that the presented method identified fault locations within 0.2 to 5% of all stuck-at faults on all lines in the circuit by probing about 0.8 to 15% internal lines.

Multiple stuck-at fault diagnosis in combinational circuits based on restricted single sensitized paths

We describe a method for multiple stuck-at fault diagnosis in combinational circuits based on restricted single sensitized paths generated by a seven-valued calculus. Our method determines the set of all possible stuck-at faults from the faulty response observed at the primary output, based on deducing internal values along the sensitized path. By using the fault-free response observed at the primary output, we remove fault-free lines along the sensitized path from the set of the candidates, by checking whether the fault-free response is prevented by the candidate fault from propagating to the primary output regardless of the presence of any other candidates. Experimental results on the benchmark circuits show that the fault locations are identified within 2-25% of all stuck-at 0 and 1 faults on all lines in the circuit with up to fourfold multiple faults without probing internal lines.<<ETX>>