Zhaohao Wang

Evaluation of spin-Hall-assisted STT-MRAM for cache replacement

Emerging spin orbit torque (SOT) promises to achieve high-speed write operation for magnetoresistive random access memory (MRAM) since it can eliminate the incubation delay of the conventional spin transfer torque (STT). Such a speed improvement allows the MRAM to be used as low-level cache in the computer architecture. Among various SOT technologies, spin-Hall-assisted STT is a potential candidate thanks to its magnetic-field-free benefit. In this work, we evaluate the potential of the spin-Hall-assisted STT-MRAM in the cache replacement. Firstly, the bit-cell parameters are obtained from the circuit-level simulation. Then, the cache evaluation and system-level simulation are performed with NVSim and Gem5 simulators. Simulation results validate the advantage of the spin-Hall-assisted STT in the write speed and energy. Moreover, for the large capacity (about >2 MB), the spin-Hall-assisted STT-MRAM is a competitive candidate for replacing the conventional SRAM-based cache.

Scaling Study of Spin-Hall-Assisted Spin Transfer Torque Driven Magnetization Switching in the Presence of Dzyaloshinskii–Moriya Interaction

Spin-hall-assisted spin transfer torque (SHA-STT) can achieve high-speed, magnetic-field-free, and high-reliable magnetization switching in a three-terminal device consisting of magnetic tunnel junctions (MTJ) above a heavy-metal. Nowadays, the development of perpendicular magnetic anisotropy drives the continuous scaling of the MTJ. In addition, an asymmetric exchange interaction called Dzyaloshinskii–Moriya interaction (DMI) inevitably exists at the heavy metal/ferromagnet interface and has a considerable influence on the magnetization dynamics. Considering these factors, in this work, we study the scaling performance of the SHA-STT driven magnetization dynamics in the presence of DMI. Simulation results demonstrate that, for nonzero DMI, the magnetization switching is activated by domain nucleation, whose mechanism is strongly dependent on the MTJ size and DMI magnitude. The critical SHE current density for magnetization switching decreases with the enlarged MTJ or enhanced DMI. In the presence of DMI, the switching time decreases with the scaling of the MTJ. Moreover, compared with the case of zero DMI, the switching speed is improved or deteriorated for the weak or strong DMI, respectively. Our work demonstrates that the MTJ size and DMI magnitude should be optimized in order to achieve a good tradeoff among a set of performance metrics of the SHA-STT devices.

A spin Hall effect-based multi-level cell for MRAM

Multi-level cell (MLC) is an efficient solution to improve the storage density of the MRAM. However, the conventional spin transfer torque-based MLC (STT-MLC) suffers from the performance bottlenecks such as high write energy and complicated two-step operation. In this work, we propose a spin Hall effect-based MLC (SHE-MLC) to overcome these bottlenecks. In the SHE-MLC structure, the write current does not pass the MTJ, which avoids the barrier breakdown and reduces the write energy. Moreover, the written data is only dependent on the direction of the write current, thus the two-step operation is not required. Simulation results demonstrate that, under the same access transistor size, e.g. 600 nm, the proposed SHE-MLC can achieve 55× faster write operation and 58× lower write energy than the conventional STT-MLC.

Size dependence of the spin-orbit torque induced magnetic reversal in W/CoFeB/MgO nanostructures

The spin-orbit torque (SOT) induced magnetic switching in structures such as Hall bars cannot be well explained with the macrospin model. The switching process is affected by the domain wall (DW) dynamics. In previous studies, some observed phenomena, such as intermediate states appearing during the magnetic switching of the Hall bar structure and asymmetric switching currents in two directions, were not well explained. In this letter, by studying the SOT induced magnetic switching in W/CoFeB/MgO nanostructures with different size, these phenomena are demonstrated to be governed by the DW propagations in nanowires and asymmetric DW pinnings at the Hall cross. The size dependence of the switching current is observed and explained with the DW depinning model. These studies provide an approach to detect the properties of the structure, such as the quantification of the spin Hall angle in the heavy metal layer.The spin-orbit torque (SOT) induced magnetic switching in structures such as Hall bars cannot be well explained with the macrospin model. The switching process is affected by the domain wall (DW) dynamics. In previous studies, some observed phenomena, such as intermediate states appearing during the magnetic switching of the Hall bar structure and asymmetric switching currents in two directions, were not well explained. In this letter, by studying the SOT induced magnetic switching in W/CoFeB/MgO nanostructures with different size, these phenomena are demonstrated to be governed by the DW propagations in nanowires and asymmetric DW pinnings at the Hall cross. The size dependence of the switching current is observed and explained with the DW depinning model. These studies provide an approach to detect the properties of the structure, such as the quantification of the spin Hall angle in the heavy metal layer.

Reconfigurable processing in memory architecture based on spin orbit torque

Data intensive workloads increase significantly bandwidth and power pressures to the memory system. One possible solution is processing-in-memory (PIM) which moves several logic components into the main memory to accelerate the logic computation. Recently, the concept of processing-in-nonvolatile-memory (PINVM) was proposed to against the technology issue in which the DRAM and logic technology require different metal layer. In addition, PINVM has the potential to mitigates the thermal influence of 3D-technology based PIM. Spin-orbit-torque (SOT) Magnetoresistive Random Access Memory (MRAM) is one of promising NVMs with high energy-efficiency, fast switching, separate read/write paths etc. In this paper, we propose a concept of reconfigurable processing-in-SOT MRAM (PISOTM) architecture to integrate reconfigurable logic into non-volatile memory. We extend the existing main memory interface and modify the controller to obtained various arithmetic function. Several dataintensive workloads are selected to evaluate the performance of our proposed PISOTM architecture. The simulation results show that the proposed architecture can achieve high-speedup improvement.

Advanced Low Power Spintronic Memories beyond STT-MRAM

Until now, spin transfer torque magnetic random access memory (STT-MRAM) has drawn considerable R&D interest worldwide. A number of companies and universities are currently involved in this promising technology. In 2016, Everspin released the first 256M STT-MRAM chip, indicating the commercialization and application of STT-MRAM. Nevertheless, STT-MRAM still has some intrinsic limitations, such as dynamic write power and speed, compared with CMOS-based memory technologies. Following the technical evolution process from toggle-MRAM to STT-MRAM, the continuous pursuit of high performance, high density, low power and scalability, drives the intensive R&D of new memory technologies. In this paper, we will show the recent progress in advanced spintronic memories beyond STT-MRAM, such as the spin Hall effect (SHE)-driven and voltage-driven MRAMs. These advanced MRAM technologies do have some unique advantages compared with STT-MRAM, but they also suffer from new design and fabrication challenges. In addition, we will present the latest research in emerging spintronic devices, e.g., magnetic skyrmions, which are potential as information carriers in future spintronic memories, e.g., racetrack memory.

Modeling for Spin-FET and Design of Spin-FET-Based Logic Gates

Spintronics-based devices and circuits attract massive research interest from both academia and industry. A number of the devices and logic circuits have been proposed such as spin-based magnetic tunnel junction and all spin logic gate. A fundamental spin-based device, spin field-effect transistor (spin-FET) is one of the most interesting spin-based devices to address the power issue of semiconductor transistors which is still a research focus. In this paper, we first present an electrical model for the spin-FET based on both theoretical and experimental results. The theories of spin injection and detection are considered by a current driver of the spin-FET. Gate voltage modulation following Datta–Das theory is combined with the experimental results from several works of literature. Afterward, through the dc analysis of two spin-FETs with different channel materials, we demonstrate that the channel using InAs is a better choice to make a feasible spin-FET. The channel length is also optimized by the comparison of simulation results. Finally, a local geometry spin-FET model suitable for logic design is implemented with Verilog-A language and integrated on Cadence platform. Using our model, a low-power inverter is designed based on the concept of complementary spin-FET, and a logic circuit is proposed to implement AND and NOR logic functions. Simulation results validate the behaviors of the logic circuits and availability of our model.

Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective

With the rapid increase of leakage currents, non-volatile memories have become competitive candidates in the next-generation computer architecture. Among them, STT-MRAM shows great promise in working memory with high density, high speed and tremendous endurance, etc. However, based on our investigations, the dynamic write power and read reliability are two critical challenges of STT-MRAM. In this work, we propose a synergistic pseudo-differential sensing (PDS) framework that employs device, circuit and architectural techniques to address these challenges. In specific, three design techniques, including cell cluster, asymmetric sensing amplifier and self-error-detection-correction, are proposed to implement the PDS framework. We show that the holistic device-circuit-architecture cross-layer co-design enables STT-MRAM to be utilized in the cache memory, benefiting from the improved density, reliability and energy-efficiency. Our experimental results show that the proposed PDS scheme improves the read margin by ∼35.6 percent, reduces the area, read latency, read energy, write latency and write power by ∼46.7, ∼9.8, ∼30.3, ∼2.3 and ∼31.1 percent respectively, compared with the typical 1T1MTJ cell structure for the cache capacity of 8 MB. In addition, the proposed PDS scheme reduces the dynamic energy by ∼32.9 percent and leakage energy by ∼830 percent, improves the IPC by ∼1.3 percent and miss rate by ∼36.9 percent respectively, compared with conventional SRAM based cache.