Karthik Chandrasekaran

Surface-Potential Solution for Generic Undoped MOSFETs With Two Gates

We present a rigorously derived analytical Poisson solution for undoped semiconductors and apply the general solution to generic MOSFETs with two gates, unifying different types such as silicon-on-insulator (SOI) and symmetric and asymmetric double gate (s-DG and a-DG) structures. The Newton-Raphson method is used to solve surface-potential equations resulting from the application of boundary conditions to the general Poisson solution, with an initial guess that is very close to the exact solution. The universal initial guess can be used as an approximate explicit solution for fast evaluation, while the iterative solution can be used for benchmark tests. The results demonstrate the unification of surface-potential solutions having an accuracy of 10-15 V for SOI, a-DG, and s-DG MOSFETs, which are achieved within two to six iterations. Furthermore, the explicit solution yields less than 3.5% error for back-to-front-gate oxide thickness ratios larger than 25

A Compact Model Satisfying Gummel Symmetry in Higher Order Derivatives and Applicable to Asymmetric MOSFETs

This paper presents a new concept for the MOSFET saturation voltages at the drain and source sides referenced to bulk, and applies them to the popularly used smoothing functions for the effective drain-source voltage (Vds,eff ). The proposed model not only builds in physically all the terminal-bias variations, but is also extended to include source/drain asymmetry in real devices in a single-core compact model. The new model resolves a key bottleneck in existing models for passing the Gummel symmetry test (GST) in higher order derivatives, which has to be traded off for the geometry-dependent Vds,eff smoothing parameter. The complete drain-current model, including the effects of velocity saturation and overshoot as well as source/drain series resistance, has also been reformulated with the same ldquobulk-referencingrdquo concept. It is shown that the proposed model passes the GST in all higher order derivatives without any constraint on the value of the smoothing parameter. It also demonstrates potential extension to modeling asymmetric MOSFETs, which is becoming an important model capability.

Explicit compact surface-potential and drain-current models for generic asymmetric double-gate metal-oxide-semiconductor field-effect transistors

In this paper, explicit surface potentials for undoped asymmetric-double-gate (a-DG) metal–oxide–semiconductor field-effect transistors (MOSFETs) suitable for compact model development are presented for the first time. The model is physically derived from Poissons equation in each region of operation and adopted in a unified regional approach. The proposed model is physically scalable with oxide/channel thicknesses and has been verified with generic implicit solutions for independent gate biases as well as for different gate/oxide materials. The model is extendable to silicon-on-insulator (SOI) and symmetric-DG (s-DG) MOSFETs. Finally, a continuous, explicit drain-current equation has been derived on the basis of the developed explicit surface-potential solutions.

Single-piece polycrystalline silicon accumulation/depletion/inversion model with implicit/explicit surface-potential solutions

A single-piece analytical equation for the surface potential at the polycrystalline-silicon (poly-Si) gate of a metal-oxide-semiconductor field-effect transistor is presented, which accounts for the poly-accumulation, poly-depletion, and poly-inversion effects. It is shown that the model accurately describes the physical behavior of the surface potentials, gate charge, and capacitance, with smooth transitions, which has been verified with iterative, explicit, and numerical solutions. The proposed model can be used in implicit or explicit surface-potential-based formulations.

Extraction of physical parameters of strained silicon MOSFETs from C-V measurement

This paper presents a methodology for extraction of the physical parameters of strained-silicon MOSFET from one capacitance-voltage (C-V) measurement based on physics-based compact model and conventional C-V characterization techniques. The extracted physical parameters (such as strained-silicon layer thickness and doping as well as conduction band offset) are used to create a numerical (Medici) device structure, from which the simulated C-V data is compared with the measured data as well as that from the compact model (Xsim), which validates the extraction technique. The proposed approach provides a simple yet physical means to probe into strained-silicon MOSFFET structures useful for characterize and model these devices, which are emerged as promising candidates for the enhancement and extension to conventional bulk-Si CMOS technology.

Compact gate-current model based on transfer-matrix method

We present a compact gate-current model based on the scattering matrix method for metal-oxide-semiconductor devices. The analytical integration of the tunneling current over the incident energy is simplified by making use of the single tunneling energy approximation, and the model error is further reduced by introducing different effective conduction band edges for the supply function and for the transmission coefficient function. Results calculated by the proposed model agree with the experimental data with satisfactory accuracy.

Implicit Analytical Surface/Interface Potential Solutions for Modeling Strained-Si MOSFETs

A new technique for calculating surface and interface potentials in heterostructure MOSFETs such as strained-Si/SiGe using an internal iteration approach is presented. It is based on the unified regional approach with coupled iterative potential solutions at the surface and heterostructure interface, and it has been applied to modeling strained-Si/SiGe MOSFETs charge and capacitance in all bias regions, scalable for Ge mole fraction, strained-Si and SiGe layer thicknesses and doping. The formulations are shown for a buried-channel nMOSFET, and the approach to the solutions is generic to all heterostructures, which exhibit confinement of carriers at the different interfaces

Xsim: unified regional approach to compact modeling for next generation CMOS

This paper describes the approaches in the development of Xsim, a unified regional threshold-voltage-based model for deep-submicron MOSFETs. In comparison to popular surface-potential-based models, our approach has the advantages of correlation to technology data, minimum data and one-iteration extraction, single-piece charge models from accumulation to strong inversion with extendibilily to poly-depletion and strained-Si, as well as selectable accuracy with the same parameter set.

Graded index substrate integrated waveguide based directional coupler

A novel graded index (GRIN) based substrate integrated waveguide (SIW) directional coupler is proposed for bandwidth enhancement. The suppression of higher order modes in the coupling region of the directional coupler is achieved by reduction in the permittivity in the coupling region by the utilization of GRIN substrate. An enhancement in the fractional bandwidth of 7% is achieved by proposed directional coupler based on GRIN SIW substrate as compared to the conventional SIW based coupler. The proposed coupler prototype bandwidth is 49% (8.5 GHz–14GHz).

A compact two-bit metamaterial inspired phase modulated chipless RFID

A compact passive two-bit metamaterial based phase-modulated chipless RFID tag at 2.4GHz is presented. The chipless RFID tag consists of a monopole antenna and CRLH delay lines operating in the left-handed (LH) region with distributed digital phase modulating sections. A Quadrature Phase Shift Key (QPSK) is implemented using the four phase modulating sections having unique input reflection coefficients corresponding to the four symbols. The dimension of the chipless tag with two phase modulating sections at 2.4GHz is 1.12λ0×0.16λ0×0.00648λ0. A footprint reduction of 22% is achieved in comparison to the conventional chipless RFID tags. Measured and simulated results show that the proposed RFID chipless tag delivers the required performance of detection with four unique symbols with compact size.