Zin Yamazaki

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems

As 40Gb/s optical communication systems enter the commercial stage, the transceiver, which is a key component of these systems, requires lower power dissipation, a size reduction, and a wider frequency range to meet the requirements of several standards, such as OC-768/STM-256 (39.8Gb/s), OTU-3 (43.0Gb/s), and 4×10GbE-LANPHY (44.6Gb/s). 40Gb/s transceivers have already been reported in SiGe-based technology.However, they dissipate more than 10W in total and do not support 39.8-to-44.6Gb/s wide-range operations [1–2]. There have been recent reports on CMOS transceivers, but their speed performance is still less than 40Gb/s and their output signal suffers from large jitter [3–5]. In this paper, 40Gb/s SFI-5-compliant TX and RX chips in 65nm CMOS technology consume 2.8W each. This low power dissipation allows for a small and low-cost plastic BGA package. The TX has a full-rate clock architecture that is based on a 40GHz VCO, a 40Gb/s retiming D-FF, and 40GHz clock-distribution circuits that lead to a low jitter of 0.57psrms and 3.1pspp at 40Gb/s. A 40/20GHz clock-timing-adjustment circuit based on a phase interpolator is used to ensure wide-range error-free operations (BER ≪ 10−12) at 39.8 to 44.6Gb/s. A quadruple loop architecture is introduced in the CDR circuit of the RX, resulting in a 38Gb/s error-free operation (BER ≪ 10−12) at 231−1 PRBS with a low rms jitter of 210fs in the recovered clock.

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems

A fully integrated 40 Gb/s transmitter and receiver chipset with SFI-5 interface is implemented in a 65 nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides good jitter performance with a 40 GHz full-rate clock architecture that alleviates pattern-dependent jitter and eliminates duty cycle dependence. The measured RMS jitter on the output is 570 fs to 900 fs over the range of 39.8 Gb/s to 44.6 Gb/s with a 231-1 PRBS pattern. The receiver chip operates over the range of 37 Gb/s to 41 Gb/s. The measured RMS jitter on the recovered clock is 359 fs to 450 fs. By taking advantage of CMOS technology, each chip achieves low power consumption of 2.8 W and full integration of SFI-5 functions, PRBS generators/error checkers, a DPSK precoder/decoder, and control interfaces in a 4.9 × 5.2 mm2 die.

40-Gb/s optical receiver IC chipset - including a transimpedance amplifier, a differential amplifier, and a decision circuit - using GaAs-based HBT technology

GaAs-based HBTs with an InGaP emitter were used to develop key components of a 40-Gb/s optical receiver: a transimpedance amplifier, a differential main amplifier, and a decision circuit. The frequency response of the transimpedance amplifier was flattened by inserting an RC series circuit at the input stage. As a result, the transimpedance amplifier module produced a well-opened 43-Gb/s eye diagram with 400 mVp-p dynamic range. The differential main amplifier and the decision circuit produced 43-Gb/s eye diagrams with a large dynamic range of 700 mVp-p, which is the first 40-Gb/s demonstration using GaAs-based HBTs. These three ICs are thus applicable to a 40-Gb/s optical receiver.

Over-100-Gb/s 1:2 Demultiplexer Based on InP HBT Technology

A 1:2 demultiplexer (DEMUX) IC based on InP HBT technology and operating over 100 Gb/s was developed. This IC provides high-speed operation with high signal quality and a wide timing margin by means of broadband impedance matching with double terminations and interconnection lines with a low phase constant in the data and clock distributions. It also obtains excellent eye openings with 550-mVp-p output voltage swings, less than 600-fs rms jitter, and error-free operation for 231 -1 at a data rate of 100 Gb/s. Moreover, mounted in a module, the DEMUX IC chip enables module operation at a data rate of 110 Gb/s. To the best of our knowledge, this is the highest data rate yet reported for DE-MUXs.

110Gb/s multiplexing and demultiplexing ICs

A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.

Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry

We implemented a low-voltage latch circuit topology in a full-rate 4:1 multiplexer (MUX) using InP-HBT technology. The proposed latch circuitry incorporates parallel current switching together with inductive peaking a combination that makes it suitable for over-40-Gb/s operation at supply voltages ranging from 1.5 to 1.8 V. The full-rate 4:1 MUX provided 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. The D-flip/flop (D-F/F) based on this latch circuitry provided 50-Gb/s D-F/F operation at a supply voltage as low as 1.5 V. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110Gb/s with a 1.8-V supply voltage. The latch circuitry should help enable development of a low-voltage 40-Gb/s full-rate module which can be seamlessly connected with high-speed CMOS I/O circuits.

An 80-Gb/s 2.7-V/sub p-p/ driver IC based on functional distributed circuits for optical transmission systems

A driver IC based on InP HBTs with a new circuit topology - called functional distributed circuit (FDC) - for over 40-Gb/s optical transmission systems has been developed. The FDC topology enables both wider bandwidth and digital functions. The distributed differential amplifier stage in the developed driver IC exhibits 2.4-V/sub p-p/ output voltage swings (differential output: 4.8 V/sub p-p/) and good eye openings at 50 Gb/s. Integrated with a 2:1 selector, the driver IC produces 2.7-V/sub p-p/ output voltage swings (differential output: 5.4 V/sub p-p/) with high signal quality at 80 Gb/s. This is equivalent to the highest data rate operation yet reported. These results indicate that the FDC has the potential to realize high-speed and functional ICs for over 40-Gb/s transmission systems.

A 100-Gb/s 1:2 Demultiplexer

A 100-Gbit/s 1:2 demultiplexer (DEMUX) has been developed using InP HBT technology. The IC features broadband impedance matching with double terminations and transmission lines with a low phase constant in the data and clock distributions to obtain high signal quality and a large timing margin. Excellent eye diagrams with 550-mVp-p output voltage swings and 600-fs rms jitter were obtained. To the best of our knowledge, this is the highest data rate operation yet reported. Moreover, error-free operation for 231 - 1 at 100-Gb/s has been achieved