Shigeki Wada

Device layer transferred poly-Si TFT array for high resolution liquid crystal projector

An active-matrix liquid-crystal light valve (LCLV) for a high-resolution projector, using device layer transfer technology, is proposed. This LCLV will not require high-density interconnection between bus lines and Si IC drivers. To confirm the validity of this proposal, a high-performance poly-Si TFT (thin-film transistor) array with 480*768 pixels in 80 mm diagonal has been fabricated on an oxidized Si wafer. This TFT has a triple-gate structure for obtaining a high on/off current ratio and buried-isolated-pixel-electrode (BIP) structure and ITO barrier metal for reducing defects. This TFT array was transferred onto transparent glass substrate using device layer transfer technology, and the liquid-crystal projector was successfully realized.<<ETX>>

A 40-Gb/s CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback

40-Gb/s clock and data recovery (CDR) circuit with an integrated high-precision eye-opening monitor (EOM) circuit and an adaptive control scheme for optimizing the data decision point are presented. An adaptive decision-point control (ADPC) scheme using the EOM feedback overcomes the time-varying waveform distortion due to transmission impairment, which causes severe degradation of bit-error-rate (BER) performance in high-speed (>40 Gb/s) data link systems. A 2.5 times 2.0-mm prototype chip is implemented in 0.18 -mum SiGe BiCMOS technology. The power consumption is 1.6 W with a +3.3-V supply voltage. Stable CDR operation with low-jitter performance (189 fs-rms) and the ADPC scheme using EOM feedback are demonstrated at 40 Gb/s. For a 30% duty-distorted 53 -mV signal, the proposed ADPC scheme drastically reduces the BER to le-12 compared to that (2e-7) without adaptive control. The experimental results demonstrate that the proposed CDR circuit greatly improves BER performance and provides robust CDR operation in high-speed data link systems.

40-Gb/s optical receiver IC chipset - including a transimpedance amplifier, a differential amplifier, and a decision circuit - using GaAs-based HBT technology

GaAs-based HBTs with an InGaP emitter were used to develop key components of a 40-Gb/s optical receiver: a transimpedance amplifier, a differential main amplifier, and a decision circuit. The frequency response of the transimpedance amplifier was flattened by inserting an RC series circuit at the input stage. As a result, the transimpedance amplifier module produced a well-opened 43-Gb/s eye diagram with 400 mVp-p dynamic range. The differential main amplifier and the decision circuit produced 43-Gb/s eye diagrams with a large dynamic range of 700 mVp-p, which is the first 40-Gb/s demonstration using GaAs-based HBTs. These three ICs are thus applicable to a 40-Gb/s optical receiver.

An ultra-low-power-consumption high-speed GaAs 256/258 dual-modulus prescaler IC

This paper describes a GaAs divide-by-256/258 dual-modulus static prescaler IC. The prescaler has a pulse swallow counter-type architecture and quasi-differential switch flip-flop (QD-FF) as its basic circuit architecture. For the input buffer circuit, we have developed a circuit that we call a Source coupled push-pull circuit (SCC), which can generate high-frequency complementary signals from a single phase signal at a low supply voltage. The IC operates at up to 14.5 GHz with a power consumption of 22 mW. The power consumption is 1/100 that of a previously reported prescaler.

Compensation for PMD-induced time-variant waveform distortions in 43-Gbit/s NRZ transmission by ultra-wideband electrical equalizer module

We have successfully demonstrated error-free transmission of 43-Gbit/s NRZ WDM signals over a 405-km SMF having a maximum of 15.6-ps DGD with our newly-developed equalizer. The equalizer removes fatal BER-degradations from rapidly time-variant waveform distortions

110Gb/s multiplexing and demultiplexing ICs

A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.

An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FFs. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers.

A 40Gb/s CDR with Adaptive Decision-Point Control Using Eye-Opening-Monitor Feedback

In high-speed data link systems of over 40Gb/s, the data decision point in the CDR circuit is not often the optimum position of the eye diagram. The CDR circuit is fabricated using a 0.18 mum SiGe BiCMOS process. The ft and fmax are 200 GHz and 180 GHz, respectively. To overcome a severe degradation of BER performance due to this misalignment, a 40 Gb/s CDR circuit integrated with an adaptive decision-point control scheme by using an eye-opening monitor feedback is developed. The key approaches are 40 Gb/s high-precision eye-opening monitor (EOM) circuit to detect an optimum decision point, an adaptive decision-point control (ADPC) scheme by using the EOM feedback, a decision- point adjustable self-aligned phase detector to achieve the ADPC operation. The combination of these approaches improves both the BER performance and the stability of CDR operation.

A 27/GHz/151 mW GaAs 256/258 dual-modulus prescaler IC with 0.1 /spl mu/m double-deck-shaped (DDS) gate E/D-HJFETs

We have developed 0.1-/spl mu/m double-deck-shaped (DDS) gate enhancement-mode (E) and depletion-mode (D) heterojunction (HJ) FET technology based upon an all-dry-etching process, which enables high current-gain cut-off frequencies (f/sub T/) in both E- and D-mode FETs above 100 GHz. We also report the first 256/258 dual-modulus prescaler IC operating above 20 GHz with low power consumption. Obtained maximum input frequency for the prescaler was 27 GHz with power consumption of 151 mW at a supply voltage of 1.2 V. This power consumption is about 1/50 of the value extrapolated from ones reported for prescalers.

0.2-/spl mu/m fully-self-aligned Y-shaped gate HJFET's with reduced gate-fringing capacitance fabricated using collimated sputtering and electroless Au-plating

This paper reports on new fully-self-aligned gate technology for 0.2-/spl mu/m, high-aspect-ratio, Y-shaped-gate heterojunction-FETs (HJFETs) with about half the external gate-fringing capacitance (C/sub f//sup rext/) of conventional Y-shaped gate HJFETs. The 0.2-/spl mu/m Y-shaped gate openings are realized by anisotropic dry-etching with stepper lithography and SiO/sub 2/ sidewall techniques instead of electron beam lithography. By introducing WSi-collimated sputtering and electroless gold-plating techniques for the first time, we have developed a high-aspect-ratio, voidless and refractory Y-shaped gate-electrode without the need for mask alignments. A fabricated 0.2-/spl mu/m gate n-Al/sub 0.2/Ga/sub 0.8/As/In/sub 0.2/Ga/sub 0.8/As HJFET shows very small current saturation voltage of 0.25 V, marked gm/sub max/ of 631 mS/mm with 6-V gate-reverse breakdown voltage, and excellent threshold voltage uniformity of 9 mV. Also, the improved rf-performance such as f/sub T/=71 GHz and f/sub max/=120 GHz is realized even with the passivation for the high-aspect-ratio gate-structure with reduced C/sub f//sup rext/. The developed technology based upon a fully-self-aligned and an all-dry-etching process provides higher performance and uniformity, thus it is very promising for high-speed and low-power-consumption digital and/or analog ICs/LSIs.