Masayuki Mamada

40-Gb/s optical receiver IC chipset - including a transimpedance amplifier, a differential amplifier, and a decision circuit - using GaAs-based HBT technology

GaAs-based HBTs with an InGaP emitter were used to develop key components of a 40-Gb/s optical receiver: a transimpedance amplifier, a differential main amplifier, and a decision circuit. The frequency response of the transimpedance amplifier was flattened by inserting an RC series circuit at the input stage. As a result, the transimpedance amplifier module produced a well-opened 43-Gb/s eye diagram with 400 mVp-p dynamic range. The differential main amplifier and the decision circuit produced 43-Gb/s eye diagrams with a large dynamic range of 700 mVp-p, which is the first 40-Gb/s demonstration using GaAs-based HBTs. These three ICs are thus applicable to a 40-Gb/s optical receiver.

Over-100-Gb/s 1:2 Demultiplexer Based on InP HBT Technology

A 1:2 demultiplexer (DEMUX) IC based on InP HBT technology and operating over 100 Gb/s was developed. This IC provides high-speed operation with high signal quality and a wide timing margin by means of broadband impedance matching with double terminations and interconnection lines with a low phase constant in the data and clock distributions. It also obtains excellent eye openings with 550-mVp-p output voltage swings, less than 600-fs rms jitter, and error-free operation for 231 -1 at a data rate of 100 Gb/s. Moreover, mounted in a module, the DEMUX IC chip enables module operation at a data rate of 110 Gb/s. To the best of our knowledge, this is the highest data rate yet reported for DE-MUXs.

Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry

We implemented a low-voltage latch circuit topology in a full-rate 4:1 multiplexer (MUX) using InP-HBT technology. The proposed latch circuitry incorporates parallel current switching together with inductive peaking a combination that makes it suitable for over-40-Gb/s operation at supply voltages ranging from 1.5 to 1.8 V. The full-rate 4:1 MUX provided 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. The D-flip/flop (D-F/F) based on this latch circuitry provided 50-Gb/s D-F/F operation at a supply voltage as low as 1.5 V. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110Gb/s with a 1.8-V supply voltage. The latch circuitry should help enable development of a low-voltage 40-Gb/s full-rate module which can be seamlessly connected with high-speed CMOS I/O circuits.

A 100-Gb/s 1:2 Demultiplexer

A 100-Gbit/s 1:2 demultiplexer (DEMUX) has been developed using InP HBT technology. The IC features broadband impedance matching with double terminations and transmission lines with a low phase constant in the data and clock distributions to obtain high signal quality and a large timing margin. Excellent eye diagrams with 550-mVp-p output voltage swings and 600-fs rms jitter were obtained. To the best of our knowledge, this is the highest data rate operation yet reported. Moreover, error-free operation for 231 - 1 at 100-Gb/s has been achieved

Low supply voltage operation of 40-Gb/s full-rate 4:1 multiplexer based on parallel-current-switching latch circuitry

We implemented new circuit topology, a parallel-current-switching latch, in a full-rate 4:1 multiplexer using InP-HBT technology. This is the first report of this technology, which resulted in 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. This voltage is as low as that of high-speed CMOS I/O circuits. This circuit topology is capable of high-speed (>40 Gb/s) selector operation with a large clock phase margin (>200 deg) at a supply voltage as low as 1.3 V using bipolar-based devices that require a relatively large supply voltage. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110 Gb/s with a 1.8-V supply voltage.