G. Van den bosch

Hot-carrier degradation phenomena in lateral and vertical DMOS transistors

The hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Upon hot-carrier stress, two different, and competing degradation mechanisms are present: channel electron mobility reduction due to interface trap formation, and injection and trapping of hot holes in the accumulation region of the transistor. It will be shown that the latter mechanism is absent in the vertical DMOS.

Spectroscopic charge pumping: A new procedure for measuring interface trap distributions on MOS transistors

An approach to the application of the charge pumping technique is proposed as a tool for the measurement of interface trap energy distributions in small area MOS transistors. The new approach is spectroscopic in nature, i.e., only one energy window is defined, and forced to move through the bandgap by changing the sample temperature. This method has the advantages of addressing a larger part of the bandgap as compared to the classical approach, of reducing the complication in the processing of the data, and of yielding information about the hole and electron capture cross sections separately. Experiments performed on both n-channel and p-channel MOS transistors reveal that, in the temperature (energy) range studied, the interface-trap distribution is slowly varying with energy and that the trap capture cross section is nearly constant over energy and temperature. >

On the geometric component of charge-pumping current in MOSFETs

A simple method of unambiguously determining the presence of any geometric component in a charge-pumping measurement by collecting this component at another node via a nearby junction is presented. With the method it has been possible to study the dependence of geometric components on device dimensions and various experimental conditions with unprecedented sensitivity. By effectively separating the two current contributions, this method can at the same time be used to reduce geometric components in the regular charge-pumping signal, thereby increasing the accuracy of the various implementations of the charge pumping (CP) technique.<<ETX>>

Temperature dependence of the channel hot-carrier degradation of n-channel MOSFET's

The generation of fast interface traps due to channel hot-carrier injection in n-channel MOS transistors is investigated as a function of stress temperature. The relative importance of the mechanisms for the generation of fast interface traps by hot electrons and hot holes is shown to be independent of the temperature. In all cases the generation of fast interface traps is slightly reduced at lower temperatures. The degradation of transistor I/sub d/-V/sub g/ characteristics, on the other hand, is strongly enhanced at lower temperatures. This is explained by a previously suggested model on the temperature dependence of the influence of the local narrow potential barrier, induced at the drain junction as a result of degradation, on the reverse-mode current characteristics. It is shown that only a minor part of the large current reduction at low temperatures can be ascribed to enhanced electron trapping. >

Characterization of Total Safe Operating Area of Lateral DMOS Transistors

The total safe operating area (SOA) of LDMOS transistors is discussed. It is shown that the transistors are subjected to different kinds of stresses, yielding a combination of electrical and thermal degradation and/or failure modes. A methodology to build the total SOA for LDMOS transistors is highlighted and is experimentally verified on a 40-V LDMOS implemented in a

Hot hole degradation effects in lateral nDMOS transistors

The degradation of a n-type lateral DMOS transistor is shown to be related to the injection of hot holes in the drift region field oxide. The saturation effects observed in the parameter shifts are reproduced by a new degradation model using the bulk current as the driving force. The dependency of the hot hole injection on the layout of the LDMOS transistors is studied.

Hot carrier degradation and time-dependent dielectric breakdown in oxides

An overview is given of our present understanding of the main degradation mechanisms acting during hot carrier and high field stress of gate oxides. A brief summary of the most important charge injection mechanisms is given, followed by a description of the damage generated under uniform charge injection. Then the degradation under more realistic operating conditions of channel hot carrier injection is reviewed, including the lifetime determination methods and the strategies to improve the hot carrier lifetime. The most important methods of oxide breakdown testing are described, as well as the basics of oxide breakdown statistics. The change of this statistics with decreasing oxide thickness, and the impact on the reliability is illustrated. The most important breakdown models and field acceleration models are reviewed as well.

On the hot-carrier-induced post-stress interface trap generation in n-channel MOS transistors

A continued fast interface trap generation is observed in n-channel MOS transistors after termination of the hot-carrier stress. The magnitude of this post-stress effect is strongly dependent on the conditions of the preceding stress, on the post-stress conditions and on the process parameters. For measurements at 293 K, a simple model is proposed which is based on the release of hydrogen by the thermal detrapping of holes, and which can explain the observed dependencies. The importance of the post-stress D/sub it/-generation is illustrated for the case of dynamic stress conditions where it can lead to an apparently deviating degradation behavior. >

Competing hot carrier degradation mechanisms in lateral n-type DMOS transistors

In this paper, the hot carrier degradation behaviour of a lateral nDMOS, processed in a 0.35 /spl mu/m compatible Smart Power Technology, is presented. It is shown that upon reverse bias stress, two different and competing degradation mechanisms occur. An attempt is made to identify the two mechanisms by analysis of the electrical data and by performing Charge Pumping (CP) experiments and TCAD simulations. A first mechanism is attributed to a decreased electron mobility due to increased carrier scattering upon Dit formation in the channel, whereas the second mechanism occurs in the gate overlapped drift region of the device and is due to hot-hole injection and trapping. The competition of both mechanisms depends strongly on the stress conditions. A model is presented.

Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory

A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (4F2, with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = 45 nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = 45 nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated.