J. Van Houdt

Comparison of scaled floating body RAM architectures

In this work, we have compared different FB-RAM architectures. Whereas highly doped PDSOI devices show high programming window and retention times for long channel devices, the SOI FinFET devices with WFIN=25 nm can be scaled down to LG=50 nm while still maintaining high cell margins and retention times. For the latter devices optimization of the write and especially read bias conditions is needed.

Quantitative and predictive model of reading current variability in deeply scaled vertical poly-Si channel for 3D memories

3D vertical poly-Si channel SONOS devices are emerging as the most prominent alternative for the 10nm nonvolatile memory technology node and beyond (1-2) provided that a significant drive current IREAD is delivered at a fixed reading gate voltage VREAD. Recently, we showed the discrete drops observed in the transfer characteristic (ID vs. VG) of 3D transistors (Fig. 1) are linked to single electron trapping in the highly defective poly-Si channel (3). This effect, in addition to low poly-Si mobility, results in low drain current measured in poly-Si channel transistors (4). As an immediate consequence, a large drain current ID variability is observed in such deeply scaled devices (Fig. 1a). In order to develop a correct model predicting this ID variability, both i) the charging component and ii) the intrinsic gm-variability have to be separately characterized and physically understood to be afterwards correctly combined. The present abstract therefore aims at developing the methodology to predict the ID distribution at fixed reading gate voltage VREAD by physical understanding of both effects: electron trapping and transconductance variations.

Scalability of Fully Planar NAND Flash Memory Arrays Below 45nm

We have simulated the coupling ratios in fully planar NAND arrays. We have shown that floating gate interference is no fundamental limitation for channel lengths down to 15 nm. The main limitation for scaling NAND arrays is the loss of control gate coupling due to fringing fields, leading to a strong increase in the programming voltage of the memory cells, even when using a 5 nm EOT IPD.

HIMOS: an attractive flash EEPROM cell for embedded memory applications

Abstract Flash EEPROMs (electrically eraseable programmable read-only memory) are the most recent products in the field of non-volatile memories. They were introduced 6 years ago to cope with the low market volumes of the expensive full featured EEPROMs. Many forecasts are stating that flash EEPROM will become in the near future one of the main technology drivers, to be used in both stand-alone memories and in embedded memory applications for ASICs [1].

Source-Side Injection Modeling by Means of the Spherical-Harmonics Expansion of the BTE

The source-side injection current in a split-gate structure has been modeled starting from the electron energy distribution along the Si-SiO2 interface provided by the deterministic solution of the Boltzmann Transport Equation in the semiconductor domain. When accounting for parallel momentum conservation, the order of magnitude of the current and its dependence on applied voltages is successfully reproduced.

Electrical Defects in Dielectrics for Flash Memories Studied by Trap Spectroscopy by Charge Injection and Sensing (TSCIS)

Introduction and purpose In the field of non-volatile memory concepts, the TANOS (TaN(or TiN)/Al2O3/Si3N4/SiO2/Si) gate stack has attracted considerable interest. For optimizing charge storage in the nitride layer and, simultaneously, optimizing the Al2O3 blocking layer, detailed information on the energy and spatial distribution of electronic defects in both layers is required. This information can be derived indirectly from modelling program/erase and reliability characteristics. However, this requires carefully chosen assumptions and fitting parameters. Recently [1], we demonstrated how Trap Spectroscopy by Charge Injection and Sensing (TSCIS) can directly provide quantitative data on trap energy and spatial position in dielectrics. These data complement the memory device characteristics and improve our understanding of device operation and reliability. In this paper, the working principle of TSCIS, together with a number of examples on materials selected for use in memory applications, are described. Measurement methodology The principle of TSCIS is illustrated in Fig. 1. On the gate of an nmos transistor, Vcharge (>Vth) is applied during time intervals with increasing length starting from ~10 ms up to 1000s. During this time, traps inside the bulk of the gate dielectric are charged by direct tunnelling of electrons from the inversion layer (Fig. 1b). In between the charging intervals, the gate voltage is switched for ~3ms to Vsense (with 0<Vsense<Vth) and the source-to-drain current ISD (with VD=0.1V) is measured (Fig. 1c). The drop of ISD at Vsense is converted into the Vth-shift using an initially measured ISDVG characteristic (Fig. 1d). This measurement methodology has been modified from and is similar to fast Vth-evaluation methods developed for minimizing the relaxation during NBTI tests, and uses the same equipment and software [2]. After discharging the sample, Vch is incremented and the sample is again charged. The final result (Fig. 2) shows the Vth-shift vs. tch measured for a range of Vch-values. Analysis The data in Fig. 2 are transformed into a trap density profile following the algorithm schematized in Fig. 3. This calculation involves WKB-approximation for determination of the tunnelling distance, a Poisson solver for finding the band bending in the presence of an arbitrary charge profile and an algorithm to keep the detailed balance between the electron injection level and trapped charge. The details of this calculation are not elaborated here, but the interpretation is schematically shown in Fig. 4a for the example of an SiO2/Al2O3 stack in the presence of an Al2O3 defect band. By increasing tch at each Vch, a trajectory in the dielectric band diagram is defined by the 1 subband energy level in the inversion layer at the corresponding tunnel distance. At low Vch, the trajectory encompasses only deep traps close to the interface, and with increasing Vch, the trajectory moves closer to the conduction band edge and further away from the interface, allowing shallow states to be occupied by injected electrons. The defect band causes, as shown in Fig. 4b and c, (1) no Vth-shift as long as the trajectory stays below the band, (2) Vth-shift vs log(tch) when the defect band is occupied by electrons, (3) saturation of the Vth-shift once the trajectory is above the defect band. When the complete data set of Fig. 2 is analysed, we can plot defect density vs. trap position and energy (Fig. 5a). We observe the defect band between ~1.7 and 2.0 eV below the Al2O3 conduction band edge. Application We have applied TSCIS to a variety of materials, each deposited on ~1 nm SiO2 interface layer, that separates the substrate from the layer under study. With thicker SiO2, too long tch is required for electrons to tunnel to the high-k dielectric. Al2O3: Crystalline Al2O3 has a typical defect band, already shown in Fig. 5a. Depending on the processing details, the trap density can vary strongly. We have independently modelled the retention behaviour in written and erased state of a floating gate memory with Al2O3 interpoly dielectric (IPD) [3]. This required the presence of an Al2O3 defect band with identical energy level and trap density, confirming the consistency of our results. In amorphous Al2O3 (with PDA @ 700C instead of 1000C) no distinct defect band signature is seen (Fig. 5b). Instead, all trap energy levels are equally present. Si3N4: Fig. 6a shows the trap distribution in LPCVD Si3N4. We observe a peak concentration of traps at ~1.65eV below the nitride conduction band edge. Furthermore, the trap concentration increases towards the center of the nitride layer. Fig. 6b illustrates how a variation of the processing conditions affects the trap density spectrum. N-rich Si3N4 has the most sharply defined density peak, while O-rich or Sirich recipes result in either very low or very high trap density distributed over a wide energy range. The TSCIS data are consistent with retention modeling as will be shown in detail in a future publication. Other materials: In [1], we demonstrated that TSCIS has sufficient resolution to detect the low (~10 cm) trap density in high-quality SiO2 after stress. The TSCIS results again agree with previous studies on flash retention. Furthermore, TSCIS is a powerful tool to study the defect properties in alternative dielectrics and timely understand their properties. As an example, we present in [4] several processing options of HfAlO as potential IPD. Future publications on GdScO, DyScO, LuAlO, and many more materials are being prepared. Conclusions Trap Spectroscopy by Charge Injection and Sensing (TSCIS) is a fast and powerful material analysis technique that provides detailed information on the trap density profile and trap energy level in dielectric materials. It has excellent resolution and is capable of distinguishing between different process-variations. These data help to understanding the operation and reliability of memory devices and facilitate a screening of new dielectric materials.

Feasibility analysis of direct tunneling through medium-κ dielectrics for embedded RAM applications

We propose medium-κ dielectrics for direct tunneling floating gate memory devices, targeting embedded RAM applications. We found that SiON offers best performance if voltage reduction overrules refresh time, while Hf-silicates would be preferred if the refresh time is more critical. Our analysis is based on a direct tunneling current model, a Response Surface Methodology and experimental data on small MOSFET’s. The impact of dielectric degradation during cycling is studied for scalability towards the 32 nm node. Introduction Floating gate (FG) MOS structures with ultra-thin SiO2 tunnel dielectric (TD) [1] have potential for embedded RAM applications. In this work, we propose the use of medium-κ materials (κ < ~10) as TD’s in a FG direct tunneling (DT) memory device for embedded RAM applications. A systematic analysis of the intrinsic performance of the FG device is carried out, using in-house developed tools. We show that medium-κ TD’s improve the performance of the DT memory. SiON is best suited for low-voltage/high-speed operation, whereas HfSiON combines very long refresh times with a low EOT. Furthermore, based on our extensive measurement database, we infer reliability-imposed scalability limits of the medium-κ DT-RAM concept to be beyond the 32 nm technology node. Device Principle The band diagrams in Fig. 1 show the device operating principle. The erased state is associated with the neutral FG, whereas the programmed state corresponds to excess electrons stored on the FG, after a positive programming pulse was applied. In order to have slow FG discharge of the programmed state, the FG potential variation should remain below the FG/substrate workfunction difference. This constraint defines the optimal range for the threshold voltage shift, ∆VT, between the two logic states. Models The Si/TD/FG structure is treated quantum-mechanically and the potentials of the stacked gate structure (Fig. 1) are determined self-consistently, using a FG capacitor model. The DT current through the TD is calculated using our recently developed model [2], based on the estimation of the lifetimes of the quasibound states in the inverted MOS channel. The model is used to fit with excellent accuracy experimental IG-VG curves (Fig. 2), from which the relevant material parameters have been consistently extracted, for (a) an InSitu Steam Generated (ISSG) oxide with Decoupled Plasma Nitridation at 10 mTorr, for 30 s (here referred to as SiON) and (b) a Hf-silicate, deposited by MOCVD, with a 1 min, 800 C NH3 PDA, following an IMEC clean [3], and with a 10 s poly activation anneal at 1000 C (HfSiON). A set of 4 factors, namely the control gate (CG) voltage (VCG), TD thickness (EOTtd), coupling factor (αG), and substrate doping (Ns), expected to be most important for the memory performance assessment of the FG structure are considered simultaneously, by using a Response Surface Methodology (RSM) [4]. We have derived RSM models for the main RAM performance factors, including the VT-shift (∆VT), the programming speed (τP), the refresh time (τR) and the read disturb time (τD), for structures with different TD’s, focusing on SiON and HfSiON, but also including conventional SiO2 (as reference) and HfO2. In all cases, the model quality regression factor exceeded 0.98, making them genuine design charts, able to account for the entire parameters space at once. Results A. The intrinsic performance We discuss the design charts for SiON, some of which are shown in Fig. 3. For programming, the CG voltage and the TD thickness are the most important factors (Fig. 3,a), whereas Ns was the least sensitive from the 4factor set, in an interval from 2.10 to 8.10 cm. Programming times of 10 ns and below can be achieved for a VT-shift of 0.5 V, for any point to the left of the dashed line. A 2.5 V CG pulse allows for 10 ns programming for a SiON of 1.42 nm EOT, whereas programming at 2 V (i.e., only 2VDD, in a 45 nm technology node) would be possible for an EOT of 1.32 nm. The coupling factor (Fig.3,b) is only of secondary importance for programming, as revealed from the ∆VT chart corresponding to τP = 10 ns. Its optimal value depends on the programming voltage, and is typically less than 0.7 (dashed line). This is the balance between the competing effects of a higher amount of the charge/cycle that has to be transferred onto the FG to achieve a given VT shift, for an increasing αG and a smaller voltage drop over the TD, which reduces the electron injection from the inverted channel, for a decreasing αG. The coupling factor is however important for improving the refresh performance, and a higher value allows for a thinner TD, at identical refresh times (Fig. 3,c). Assuming S/D overlaps similar to contemporary MOS devices, refresh times of 64 ms or longer are not compatible with TD’s enabling 10 ns low-voltage programming. The design window for 200 μs refresh time at 2.5 V programming (“ABC” in Fig. 3,c) is very narrow and requires a very high coupling factor, of more than 0.85, due to the S/D extension-dominated FG discharge (inset, Fig. 2,a). Removing the S/D overlaps by a technology workaround causes the 200 μs refresh time to be no more an issue and significantly enlarges the 64 ms design window (“ABCD”, Fig. 3,d) down to coupling factors of 0.7. Read disturb has also been investigated and read-out times of up to 1 μs are not causing more than 20 % charge loss, for read pulses as high as 1.2 V. Erasing at 10 ns is not an issue when the S/D overlap is present, while erasing in less than 100 ns is feasible when removing it. All the considered materials were subject to a similar treatment. Fig. 4 summarizes the main performance results for conventional and medium-κ TD’s. SiON is the best candidate for low-voltage embedded DT-RAM, offering about 0.7 V decrease of the programming pulse, as compared to SiO2 at similar speed and allowing for a 2VDD CG pulse at 10 ns/0.5 V-shift and with a 200 μs refresh at 1.3 nm EOT. 64 ms refresh is possible for αG’s higher than ~0.75, for a 1.4 nm EOT. HfSiON requires higher programming pulses, due to the reduced DT current. However, it has clearly superior refresh times at lower EOT’s, due to a built-in κ-asymmetry, making the tunnel barrier less sensitive to the applied bias (Reverse-VARIOT effect) [5], thus reducing the FG discharge. SiO2/HfO2 TD’s behave similar to HfSiON, however their use is questionable due to QBD limitations [6]. B. Scalability & Reliability projections Small-area (0.25x0.35μm) transistors have been subjected to positive CVS and the current through a single generated trap has been extracted, as discussed in our recent work [7]. Single-trap IV curves have been divided into clusters, using a Jarvis-Patrick nearest-neighbor partitioning algorithm [8]. Most of the traps cause a current relatively more important in the low bias range (Fig. 5,a, inset), as compared to the feature-size (F) dependent DT current. The average current of a typical IV cluster is fitted using a trapassisted tunneling (TAT) model (Fig. 5.a). This permitted extraction of the parameters of the generated traps, which were subsequently used in assessing the impact of a typical defect on the FG charge retention. For a programmed device, the electrons leak from the FG to the substrate. The contribution of the average current of a typical cluster to the total FG discharge current (at VFG<0) through the TD becomes more important when the device area is scaled down, as shown in Fig. 5,b for F down to 32 nm and adversely affects the FG charge loss (Fig. 6,a). We noticed that traps situated over the S/D overlap region draw even more current, which is one more argument in favor of a tight control of the FG to S/D overlap. The remaining VT-window is reduced as compared to the trap-free case. However, there is still a sufficient margin for a tolerated loss of the VT-window of up to 20 %, even below the 32 nm node (Fig. 6,b). Fig. 7 shows the estimated number of cycles to reach the QBD (calculated as a 1 μA current increase), for SiON and HfSiON, with F = 45 nm. The degradation in 1 cycle is determined from the time-dependent voltage drop over the TD, assuming ∆VT = 0.5 V. For the measured samples, SiON shows the best performance, with over 10 cycles. Available SiO2/HfO2 samples of ~1 nm EOT reached the QBD criterion at a 10 nscompatible VCG after very few cycles and cannot be used as a TD for DTRAM memory, with the present targets. Further statistical analysis of the trap effects is in progress. Conclusion We demonstrated that using medium-κ TD’s brings significant improvement in the performance of the DT FG memory. Ultrathin SiON allows for lowvoltage (down to 2 V) 10 ns operation, with a 200 μs refresh for about 1.3 nm EOT, or 2.5 V/10 ns/64 ms for about 1.4 nm. HfSiON offers very long retention times, combined with a thin EOT. The QBD–based endurance estimation considerably exceeds 10 cycles, and the structure shows scalability at least down to the 32 nm node, provided that the FG to S/D overlaps are well controlled, ideally removed. Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials, Kobe, 2005, -444H-4-1 pp.444-445