Tadahiro Sasaki

A 1.9 GHz SPDT switch implemented with GaN HFETs featuring two different depth-recesses in i-AlGaN

An i-AlGaN/GaN HFET structure with two different depth-recesses formed in the i-AlGaN layer is proposed for application to a 1.9 GHz SPDT switch. In the HFET structure, an ohmic contact is formed in the deep recess to reduce the contact resistance, and a Schottky gate is formed in the shallow recess to decrease the leakage current. The off-state capacitance of the HFET was 0.23 pF and the on-state resistance was 11 /spl Omega/ at a gate length of 0.7/spl mu/m and a width of 1 mm. An SPDT switch implemented with the HFETs was fabricated, and evaluated by on-wafer measurement. The maximum handling power was 34.7dBm at the device where the through FET width was 1 mm and the shunt FET width was 0.2 mm. A higher isolation than 21 dB and a low insertion loss of 1.1 dB were realized. This performance indicates that the proposed structure is promising for high-power and high-frequency RF switches.

An 8-bit slice GaAs bus logic LSI for a high-speed parallel processing system

An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7*7-mm/sup 2/ chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8- mu m WN/sub x/ gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s. >

Anomalous Substrate Current in Metal–Oxide–Semiconductor Field-Effect Transistors with Large Channel Width

Anomalously large substrate current has been observed in a metal–oxide–semiconductor field-effect transistor (MOSFET) with a large channel width of 1600 µm. The magnitude of the substrate current per unit channel width is approximately 2 orders larger than that of a MOSFET with a channel width of 100 µm when they are compared at the maxima. Furthermore, the substrate current measured as a function of gate voltage could not be fit to a typical simulation model based on the conventional theory of impact ionization. In addition to the substrate current, anomalies were also observed in the drain current and the gate leakage current measured simultaneously with the substrate current. To explain the interrelation of the anomalous phenomena, we have introduced a hypothesis in which two modes of impact ionization are excited in the respective voltage regions generating electron–hole pairs in specific directions.

A 6 K-gate GaAs gate array with a new large-noise-margin SLCF circuit

A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned lightly doped drain (LDD) structure GaAs MESFET process. Chip size was 8.0/spl times/8.0 mm/SUP 2/. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/IF. A 16-b serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers.

Primary Factor Extracted for Anomalous Decline of Drain Current in Metal–Oxide–Semiconductor Field-Effect Transistors

A statistical approach has been exploratively applied to extract an influential factor of anomalous decreases in drain current observed in metal–oxide–semiconductor field-effect transistors with large channel widths. Since negative slopes were detected in drain current vs drain voltage (Id–Vds) curves even with negligible heat quantity or density, the self-heating effect was excluded as the primary factor. In contrast, the aspect ratio of the device areas showed a significant influence. These results support the validity of a hypothesis, namely, that acoustic standing waves are excited and thereby the probabilities of impact ionizations are synchronously magnified in the devices.

Building-cell design methodology for high-speed GaAs standard-cell LSIs

A novel layout concept of Building-Cell (BC) methodology which realizes high-speed GaAs standard-cell LSIs is introduced. This methodology reduces the layout area and wiring-length, and leads to a large degree of freedom for cell placement. A GaAs data bus LSI, consisting of 3500 gates and a 75-bit register file, was designed to verify the effectiveness of this methodology, which functioned at a fast cycle time of 7 ns.<<ETX>>

Stabilized Linear Operation of CMOS Power Transistors for Si-RF Transceiver Integration

We report on stabilization of CMOS power transistors employing a new layout concept. We assume that instability of power transistors is caused by intensified impact ionization at the pinch-off channels, and that the impact ionization is synchronized with acoustic standing waves in the device area if they are designed with conventional layout configurations. In the new layout design, gate fingers are electrically connected in parallel, but thermally and geometrically isolated from one another at random intervals. The shape of the device area is deformed so that acoustic waves are scattered at the boundaries of device area surrounded by shallow trench isolation (STI). Measurements demonstrated that the stability of transistors has been improved. For example, a transistor with a gate width of 800 μm has shown the 1 dB-compression point P1dB of 15 dBm and the saturation power PSAT of 21 dBm at 2.45 GHz under a bias condition for linear operation. The results indicate that the CMOS transistors are suitable for power amplifiers, especially, for full integration of wireless transceivers.

Electromagnetic Band Gap structure for cut off of low frequency noise in 3-D printed circuit board

This paper describes the design of mushroom EBG (Electromagnetic Band Gap) structure within slit defected on power supply plane in order to control PI (power integrity) for realizing high-density multi-stacked printed circuit board. Generally, EBG structure is not suitable to block the low frequency noise around 1GHz in the printed circuit board, because EBG structure requires large area to cutoff low frequency noise. In this paper, new type of mushroom EBG structure, which has slit defect on power supply plane, to increase inductance for EBG function was proposed. By applying the new mushroom EBG structure of small patch size 10mm × 10mm × 3 pieces in the 0.9 mm thickness printed circuit board, we realized -40dB isolation at stop band frequency 0.94GHz~1.25GHz. Consequentially, the multi-stacked printed circuit board thickness could be reduced to 81% of using conventional mushroom EBG structure.

Linear CMOS power amplifiers employing a novel layout configuration for improved stability and long-term reliability

This paper presents a design and characterization of linear CMOS power amplifiers employing a new layout configuration of transistors, assuming that both unstable operation known as memory effects and degradation of power transistors are caused by hot carrier effects through thermal energy accumulation and magnified impact ionization at the pinch-off channels by acoustic phonon. The new layout concept of the power transistors has been applied in a single-chip power amplifier circuit in class AB operation using 0.13 µm standard CMOS process. High-power durability tests have revealed that the transistors of the new type are free from significant degradation even in long-term continuous operations.

Cell-shifting compaction of building-cell methodology for high-speed GaAs standard-cell LSIs

The authors propose a novel cell-shifting compaction concept for building-cell methodology to realize high-speed GaAs standard-cell LSIs. This compaction reduces the layout-area and stray capacitance and the inductance of routings, and leads to a large degree of freedom for cell placement. The cell-shifting compaction is also a valid approach for Si standard-cell LSIs.<<ETX>>