A. Tanabe

Performance Enhancement of Tunnel Field-Effect Transistors by Synthetic Electric Field Effect

In this letter, we propose a synthetic electric field (SE) effect to enhance the performance of tunnel field-effect transistors (TFETs). The novel SE-TFET architecture utilizes both horizontal and vertical electric fields induced by a gate electrode that is wrapped around an ultrathin epitaxial channel. The drain current of the SE-TFET is increased up to 100 times in comparison with those of conventional TFETs. The subthreshold slope of the SE-TFET also improved, and enhanced to 52 mV/decade by scaling the channel width and channel thickness.

First demonstration of drain current enhancement in SOI tunnel FET with vertical-tunnel-multiplication

CMOS tunnel FETs (TFETs) with vertical-tunnel-multiplication (VTM) were fabricated. VTM TFETs initiate band-to-band tunneling (BTBT) parallel to the gate electric field and effectively extend the tunnel area. Impact of the VTM was analyzed using a distributed-element circuit model, and the drain current multiplication by extended tunnel area was experimentally revealed for the first time.

Analysis of threshold voltage shifts in double gate tunnel FinFETs: Effects of improved electrostatics by gate dielectrics and back gate effects

We analyzed the threshold voltage (Vth) shift due to EOT scaling in double gate (DG) tunnel FinFETs (tFinFETs). It is found that Vth in tFinFETs has high sensitivity of EOT, which is quite different as compared with MOSFETs. We proposed a simple model which is indispensable to design the tFinFETs structure for the first time. In order to correct the Vth modulation due to EOT scaling in tFinFETs, we studied the back gate effect in independent-DG tFinFETs and revealed that the back bias is effective as is the case in the MOSFETs.

Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field, was evaluated. The TFET was fabricated by inserting a parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer. We also propose a scheme to improve the performance of the TFETs by modification of the gate and channel configurations.

Guidelines for symmetric threshold voltage in tunnel FinFETs with single and dual metal gate electrodes

We report guidelines for symmetric threshold voltage (V_th) in double gate (DG) tunnel FinFETs (tFinFETs) with single and dual metal gate electrodes. To realize the symmetric V_th=±0.2V, the work function difference (ΔΦ_m) of each gate electrode in n- and p-type tFinFETs with a nondoped Si channel must be 1.34 eV, indicating that tuning the effective work functions in the dual metal gates is difficult. By adding Ge in the channel, the work function required in Ge-channel p-tFinFETs can be reduced to 4.46 eV, furthermore, ΔΦ_m required to realize a symmetric V_th in n- and p-type tFinFETs can be as small as the minimum value of 0.28 e V. This result means that a symmetric V_th is realized in realistic dual metal gate materials by adding Ge. By using our independent DG tFinFETs with a novel source profile, a symmetric V_th can be realized in a single metal gate in a Ge channel.