J.-P. Colinge

Demonstration of the potential of accumulation-mode MOS transistors on SOI substrates for high-temperature operation (150-300 degrees C)

Measurements of accumulation-mode (AM) MOS SOI transistors in the 150-300 degrees C temperature range are reported and discussed. The increases of the threshold voltage shift and off leakage current with temperature of these SOI p-MOSFETs are observed to be much smaller than their bulk equivalents. Simple models are presented to support the experimental data.<<ETX>>

Evidence of two-dimensional carrier confinement in thin n-channel SOI gate-all-around (GAA) devices

The effect of two-dimensional electron confinement is observed in thin-film, gate-all-around SOI transistors operated at low temperature. Physical 3D confinement in a thin silicon film using the silicon/gate oxide potential barrier (in contrast to heterojunction or electrostatic confinement) is shown for the first time. In these devices volume inversion gives rise to a 2DEG, and the population of the energy subbands can be controlled by the gate voltage. The position of transconductance peaks and valleys, corresponding to the population of different subbands as the gate voltage is increased, is in good agreement with theoretical predictions.<<ETX>>

Comparison of self-heating effect in GAA and SOI mosfets

An analytical model is developed to estimate the effect of the scaling of the buried oxide on the heat flow in SOI devices. The heat evacuation is shown to follow the buried oxide thickness to the n-th power with -0.5 > n > -1, and it strongly depends on device dimensions. Three experimental independent evidences of reduced self-heating in GAA devices are provided and analyzed in the light of an analytical model. The advantage of the GAA structure is to replace the buried oxide below the channel by a back polysilicon gate that benefits for a much larger thermal conductivity. To achieve the same result in SOI devices, the buried oxide thickness should be reduced down to twice the gate oxide thickness, which unfortunately would also lead to a dramatic increase of source and drain parasitic capacitances. In the GAA transistor, on the contrary, source and drain regions still lie on the thick buried oxide layer such that those parasitic elements keep a low value.

Low temperature behaviour of submicron accumulation mode p-channel SOI MOSFETs

The conduction mechanisms of submicron accumulation mode SOI pMOSFETs are investigated for the device operation at T=77K and T=4.2K. A physical interpretation for the suppression of some current components is given. Finally, the room temperature analytical model is extended and experimentally validated for cryogenic operation analysis.

Coupling effects in high-resistivity SIMOX substrates for VHF and microwave applications

The use of high-resistivity SIMOX substrates has been proposed to enable the integration of low-loss adapted lines for MMIC applications in SOI CMOS technology. In this work we investigate the impact of the substrate resistivity on another important substrate coupling effect: the intrinsic load impedance of active transistors in amplifier configuration, which conditions the device maximum stable frequency. Related device and line modelling aspects are also discussed.

NOVEL TESC BIPOLAR TRANSISTOR APPROACH FOR A THIN-FILM SILICON-ON-INSULATOR SUBSTRATE

Silicon-on-Insulator (SoI) technology offers an advanced electronic material structure suitable for realisation of a high performance bipolar transistor (BT). In this work, we demonstrate a route to a high performance thin-film BT on SoI fabricated using Sol-CMOS process for future thin-film SoI-BiCMOS circuits. The proposed novel approach to a thin-film BT has a device structure with a highly efficient Top poly-silicon Emitter and a low resistance N+ Side-Collector (TESC). An npn TESC-BT was fabricated on an 85nm thinned silicon overlayer of SIMOX material. Good common-emitter output characteristics of the npn TESC-BT were obtained, demonstrating the viable underlying concept of a TESC approach for a bipolar transistor fabricated on thin-film SoI substrate. The evaluated lateral pinched base resistance of 4kΩ for a 20µm long TESC device is reflected in the collector current role-off at a very high current density (6000Acm−2). A reduction in the base Gummel number, as a consequence of back-gate biasing the TESC device dramatically enhances the current gain and induces drift current favourable for achieving higher ft. Under such baising conditions or with a suitable doping profile, a 2-dimensional bipolar operation can occur. The TESC device offers the potential for realising vertical bipolar operation in a very thin-film silicon overlayer by inverting the back-interface, which acts as an extended side collector, thus improving the collecting efficiency. The TESC approach to bipolar transistor in a thin-film SoI was found to be a versatile device which can sustain, both the lateral and vertical bipolar operation.