Aasutosh Dave

Demonstrating the benefits of source-mask optimization and enabling technologies through experiment and simulations

In recent years the potential of Source-Mask Optimization (SMO) as an enabling technology for 22nm-and-beyond lithography has been explored and documented in the literature.1-5 It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the source, which leads to improved lithographic performance. These efforts have driven the need for improved controllability in illumination5-7 and have pushed the required optimization performance of mask design.8, 9 This paper will present recent experimental evidence of the performance advantage gained by intensive optimization, and enabling technologies like pixelated illumination. Controllable pixelated illumination opens up new regimes in control of proximity effects,1, 6, 7 and we will show corresponding examples of improved through-pitch performance in 22nm Resolution Enhancement Technique (RET). Simulation results will back-up the experimental results and detail the ability of SMO to drive exposure-count reduction, as well as a reduction in process variation due to critical factors such as Line Edge Roughness (LER), Mask Error Enhancement Factor (MEEF), and the Electromagnetic Field (EMF) effect. The benefits of running intensive optimization with both source and mask variables jointly has been previously discussed.1-3 This paper will build on these results by demonstrating large-scale jointly-optimized source/mask solutions and their impact on design-rule enumerated designs.

22-nm-node technology active-layer patterning for planar transistor devices

As the semiconductor device size shrinks without a concomitant increase of numerical aperture (NA) and refractive index of the immersion fluid, printing 22-nm-technology devices presents challenges in resolution. Therefore, aggressive integration of a resolution enhancement technique (RET), design for manufacturability (DFM), and layer-specific lithographic process development are strongly required in 22-nm-technology lithography. We show patterning of an active layer of a 22-nm-node planar logic transistor device, and discuss achievements and challenges. Key issues identified include printing tight pitches, isolated trench, and 2-D features while maintaining a large lithographic process window across the chip while scaling down the cell size. Utilizing NA=1.2, printing of the static random access memory (SRAM) of a cell size of 0.1 µm2 and other critical features across the chip with a process window are demonstrated.

22 nm technology node active layer patterning for planar transistor devices

As the semiconductor device size shrinks without concomitant increase of the numerical aperture (NA=1.35) or index of the immersion fluid from 32 nm technology node, 22 nm patterning technology presents challenges in resolution as well as process window. Therefore, aggressive Resolution Enhancement Technique (RET), Design for Manufacturability (DFM) and layer specific lithographic process development are strongly required. In order to achieve successful patterning, co-optimization of the design, RET and lithographic process becomes essential at the 22 nm technology node. In this paper, we demonstrate the patterning of the active layer for 22 nm planar transistor device and discuss achievements and challenges in 22 nm lithographic printing. Key issues identified include printing tight pitches and 2-D features simultaneously without sacrificing the cell size, while maintaining large process window. As the poly-gate pitch is tightened, the need for improved corner rounding performance is required inorder to ensure proper gate length across the entire gate width. Utilizing water immersion at NA=1.2 and 1.35, we will demonstrate patterning of the active layer in a 22 nm technology node SRAM of a bit-cell having a size of 0.1 μm2 and smaller while providing large process window for other features across the chip. It is shown that highly layer-specific and design-aware RET and lithographic process developments are critical for the success of 22 nm node technology.

Applicability of global source mask optimization to 22/20nm node and beyond

Source-mask optimization (SMO) in optical lithography has in recent years been the subject of increased exploration as an enabler of 22/20nm and beyond technology nodes [1-6]. It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the source and mask, which yields improved lithographic performance. This paper will demonstrate the value of SMO software in resolution enhancement techniques (RETs). Major benefits of SMO include improved through-pitch performance, the possibility of avoiding double exposure, and superior performance on two dimensional (2D) features. The benefits from only optimized source, only optimized mask, and both source and mask optimized together will be demonstrated. Furthermore, we leverage the benefits from intensively optimized masks to solve large array problems in memory use models (MUMs). Mask synthesis and data prep flows were developed to incorporate the usage of SMO, including both RETs and MUMs, in several critical layers during 22/20nm technology node development. Experimental assessment will be presented to demonstrate the benefits achieved by using SMO during 22/20nm node development.

Pushing the limits of RET with different illumination optimization methods

As we proceed to 22 nm technology node without any advancement from the front of numerical aperture or EUV, it has become really challenging to come up with a robust solution to confront resolution and process window. At this stage along with litho friendly design and new advent in lithographic processes, it has become vital to acquire highly optimized resolution enhancement technology (RET). In this paper, we review different realm of illumination optimization techniques with combination of currently available source shapes along with pixilated source optimization. Different source shapes are tested over various technology designs such as 32 nm and 22 nm designs for better fidelity and process window. We optimize different source shapes manually and also evaluate fidelity with optimized pixilated source. The results demonstrate how we can achieve better resolution for some layout patterns with different illumination optimization methods.

The assessment of the impact of mask pattern shape variation on the OPC-modeling by using SEM-Contours from wafer and mask

As design rules shrink, Optical Proximity Correction (OPC) becomes complicated. As a result, measurement points have increased, and improving the OPC model quality has become more difficult. From the viewpoint of decreasing OPC calibration runtime and improving OPC model quality concurrently, Contour-based OPC-modeling is superior to CD-based OPC-modeling, because Contour-based OPC-modeling uses shape based rich information. Hence, Contour-based OPC-modeling is imperative in the next generation lithography, as reported in SPIE2010. In this study, Mask SEM-contours were input into OPC model calibration in order to verify the impact of mask pattern shape on the quality of the OPC model. Advanced SEM contouring technology was applied to both of Wafer CD-SEM and Mask CD-SEM in examining the effectiveness of OPC model calibration. The evaluation results of the model quality will be reported. The advantage of Contour based OPC modeling using Wafer SEM-Contour and Mask SEM-Contour in the next generation computational lithography will be discussed.

Calibrating OPC model with full CD profile data for 2D and 3D patterns using scatterometry

The ability to manage critical dimensions (CDs) of structures on IC devices is vital to improving product yield and performance. It is challenging to achieve accurate metrology data as the geometries shrink beyond 40 nm features. At this technology node CDSEM noise and resist LER are of significant concerns1. This paper examines the extendibility of scatterometry techniques to characterize structures that are close to limits of lithographic printing and to extract full profile information for 2D and 3D features for OPC model calibration2. The resist LER concerns are diminished because of the automatic averaging that scatterometry provides over the measurement pad; this represents a significant added value for proper OPC model calibration and verification. This work develops a comparison matrix to determine the impact of scatterometry data on OPC model calibration with conventional CDSEM measurements. The paper will report test results for the OPC model through process data for accuracy and predictability.

Influence of the illumination source on model-based SRAF placement

Sub-Resolution Assist Features (SRAFs) have been extensively used to improve the process margin for isolated and semi-isolated features. It has been shown that compared to rule-based SRAFs, model-based placement of SRAFs can result in better overall process window. Various model-based approaches have been reported to affect SRAF placements. Even with model-based solutions, the complexity of two-dimensional layouts results in SRAF placement conflicts, producing numerous challenges to optimal SRAF placement for each pattern configuration. Furthermore, tuning of SRAF placement algorithms becomes challenging with varying patterns and sources [1-3]. Recently, pixelated source in optical lithography has become the subject of increased exploration to enable 22/20 nm technology nodes and beyond. Optimization of the illumination shape, including free-form pixelated sources, has shown performance gains, compared to standard source shapes [4-6]. This paper will demonstrate the influence of such different free-form sources as well as conventional sources on model-based SRAF placement. Typically in source optimization, the selection of the optimization patterns is exigent since it drives the source solution. Small differences in the selected patterns produce subtle changes in the optimized source shapes. It has also been previously reported that SRAF placements are significantly dependent on the illumination [1]. In this paper, the impact of changes in the design and/or source optimization patterns on the optimized source and hence on the SRAF placement is reported. Variations in SRAF placements will be quantified as a function of change in the free-form sources. Lithographic performance of the different SRAF placement schema will be verified using simulation.

Impact of illumination on model-based SRAF placement for contact patterning

Sub-Resolution Assist Features (SRAFs) have been used extensively to improve the process latitude for isolated and semi-isolated features in conjunction with off-axis illumination. These SRAFs have typically been inserted based upon rules which assign a global SRAF size and proximity to target shapes. Additional rules govern the relationship of assist features to one another, and for random logic contact layers, the overall ruleset can become rather complex. It has been shown that model-based placement of SRAFs for contact layers can result in better worst-case process window than that obtained with rules, and various approaches have been applied to affect such placement. The model comprehends the specific illumination being used, and places assist features according to that model in the optimum location for each contact hole. This paper examines the impact of various illumination schemes on model-based SRAF placement, and compares the resulting process windows. Both standard illumination schemes and more elaborate pixel-based illumination pupil fills are considered.

Introducing a novel flow to estimate challenges encountered while transitioning from RET development to manufacturable solution

Source Mask Optimization (SMO) has become an integral part of resolution enhancement techniques (RET) for almost all critical layers at advanced technology nodes. Over the past couple of years, various flows have emerged for integrating SMO into mainstream RET selection. These flows revolve mainly around clip selection, resist model, verification and analysis metrics, design rule optimization, and so on. There has also been strong emphasis on the quality of mask that is conjugated for source selection process. All these variations in analysis and rigorous simulations for flow selection are critical but they also create a bottleneck in overall RET development. In this paper, we demonstrate an initial RET development flow for 20 nm technology with emphasis on quantifying benefits coming from source and mask. We also report challenges that are encountered in the foundry environment when moving from RET development to production. In conclusion, we demonstrate a reliable solution that could be integrated early in RET development and easily adapted for a production environment.