Ryoung-han Kim

The use of EUV lithography to produce demonstration devices

In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1). This device fabrication exercise required the development of rule-based OPC to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm2, providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results. Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.

Line-edge roughness in 193-nm resists: lithographic aspects and etch transfer

We describe methods to determine transfer functions for line edge roughness (LER) from the photoresist pattern through the etch process into the underlying substrate. Both image fading techniques and more conventional focus-exposure matrix methods may be employed to determine the dependence of photoresist LER on the image-log-slope (ILS) or resist-edge-log-slope (RELS) of the aerial image. Post-etch LER measurements in polysilicon are similarly correlated to the ILS used to pattern the resist. From these two relationships, a transfer function may be derived to quantify the magnitude of LER that transfers into the polysilicon underlayer from the photoresist.1 A second transfer function may be derived from power spectral density (PSD) analysis of LER. This approach is desirable based on observations of pronounced etch smoothing of roughness in specific spatial frequency ranges. Smoothing functions and signal averaging of large numbers of line edges are required to partially compensate for large uncertainties in fast-Fourier transform derived PSDs of single line edges. An alternative and promising approach is to derive transfer functions from PSDs estimated using autoregressive algorithms.

A lithographic and process assessment of photoresist stabilization for double-patterning using 172-nm photoresist curing

We have developed a unique resist stabilization process for double patterning that uses 172 nm UV curing to freeze a first photoresist pattern prior to application and patterning of a second photoresist film. 172 nm cure offers many potential advantages over other resist stabilization processes, including improved pattern fidelity vs. other cure processes and track-based implementation scenarios that are relatively simple, compact, and inexpensive. Assessment of 172 nm double imaging process requirements and limitations indicates that pattern distortions in the frozen first photoresist may arise during all 2nd patterning steps, including coating, exposure, and development. Careful optimization to maximize overall pattern fidelity is needed. Process optimization using a conventional 193 nm photoresist suggests that pattern freeze approaches based on resist cure are best suited to extremely regular structures due to line-end and other resist distortions. Nevertheless, the method allows cross-grid contact printing at lithographic k1 = 0.385.

Extreme ultraviolet lithography: From research to manufacturing

The authors explore the critical issues remaining for the introduction of extreme ultraviolet lithography (EUVL) in semiconductor manufacturing. Among all technical issues, source power appears to be the most significant challenge that the technology is facing at this time. The lack of sufficiently high-power sources integrated in the first generation of full-field commercial scanners has profound implications on the remaining issues, and therefore on the risk associated with the insertion of EUVL technology. At the core of the problem is the cost of ownership of EUVL, which depends most heavily on source power. Moreover, the lifetime of the scanner mirrors and of the masks can only be tested properly with high-power sources on these first scanners. Without the ability to perform these tests, the technology might suffer unrecoverable delays. Fortunately, there has been good progress in the development of laser-produced plasma sources, which appear to be the most capable candidates for high-power scalabili...

Lithographic metrics for the determination of intrinsic resolution limits in EUV resists

Resist resolution remains a significant issue for EUV. Strong concerns remain with the use of chemically amplified resist owing to their diffusion characteristics. Currently EUV resist development is primarily focused on large-scale screening efforts in an attempt to identify platforms showing promise in a variety of areas with resolution arguably being the parameter of highest importance at this time. The characterization of the intrinsic resolution limit of resists, however, is not a trivial issue due to practical complications such as pattern collapse and top-loss. Note that the intrinsic resist resolution limit has been claimed to be determined by the resist diffusion length and various metrics have been proposed to characterize this diffusion length as well as resist resolution. Here we investigate a variety of resolution and diffusion length metrics and study the correlation between these metrics and observed resist performance when applied to a variety of leading EUV resists. The metrics we study include iso-focal bias, line-edge-roughness correlation length, resist modulation transfer function, and corner rounding.

Post-etch LER performance of novel surface conditioner solutions

As line edge roughness (LER) becomes one of the critical lithography challenges, there is a growing interest in applying surface conditioner solutions during post-develop process to reduce LER. In this paper, we evaluated the combined effect of surface conditioners and hard bake on the post-develop LER. There is about 1nm LER reduction, as well as a significant improvement on the common process window for LER. No negative impact on CD process window was observed with the new process. In addition, preliminary etch data showed that surface conditioners have no negative impact on pattern transfer through etch.

Cure-induced photoresist distortions in double patterning

Many processes are under evaluation as simplifications to current double patterning methods. Reduction in process complexity and cost may be achieved by use of track-based photoresist stabilization methods that eliminate one etch step by allowing a second resist to be patterned over a first resist. Examples of stabilization methods using numerous curing processes have been reported. At least some resist shrinkage during stabilization appears to be generally observed for these methods. We evaluate the link between shrinkage and three-dimensional pattern distortions at line ends and elbow corners using experimental and simulation-based methods. A 172-nm UV resist curing process was used to produce controlled shrinkage ranging from 5% to 30%: shrinkage was correlated with resist distortions. At cure dose sufficient to stabilize the resist, shrinkage of approximately 23% results in measured line-end pullback and elbow displacement of approximately 16% and 13% of nominal linewidth respectively, when measured at resist half-height. Finite element analysis of resist beam structures produces shrinkage distortions that are in good qualitative and semiquantitative agreement with these measurements and thus appears to provide a provisionally general and useful method for predicting pattern distortions that arise during cure-based resist stabilization methods used in double imaging.

Overcoming the challenges of 22-nm node patterning through litho-design co-optimization

Historically, lithographic scaling was driven by both improvements in wavelength and numerical aperture. Recently, the semiconductor industry completed the transition to 1.35NA immersion lithography. The industry is now focusing on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh diffraction. Here, the IBM Alliance demonstrates the extendibility of several double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. This paper details a set of solutions that have enabled early 22 nm learning through careful lithography-design optimization.

22 nm technology node active layer patterning for planar transistor devices

As the semiconductor device size shrinks without concomitant increase of the numerical aperture (NA=1.35) or index of the immersion fluid from 32 nm technology node, 22 nm patterning technology presents challenges in resolution as well as process window. Therefore, aggressive Resolution Enhancement Technique (RET), Design for Manufacturability (DFM) and layer specific lithographic process development are strongly required. In order to achieve successful patterning, co-optimization of the design, RET and lithographic process becomes essential at the 22 nm technology node. In this paper, we demonstrate the patterning of the active layer for 22 nm planar transistor device and discuss achievements and challenges in 22 nm lithographic printing. Key issues identified include printing tight pitches and 2-D features simultaneously without sacrificing the cell size, while maintaining large process window. As the poly-gate pitch is tightened, the need for improved corner rounding performance is required inorder to ensure proper gate length across the entire gate width. Utilizing water immersion at NA=1.2 and 1.35, we will demonstrate patterning of the active layer in a 22 nm technology node SRAM of a bit-cell having a size of 0.1 μm2 and smaller while providing large process window for other features across the chip. It is shown that highly layer-specific and design-aware RET and lithographic process developments are critical for the success of 22 nm node technology.

Application of contrast enhancement layer to 193nm lithography

The feasibility of contrast enhancement layer (CEL) for extending the practical limit of 193nm lithography was studied using an analytical model, exposed latent image inside the resist, and finite difference time-domain analysis. All studies showed that the CEL is applicable to 193nm regime and beneficial for obtaining a contrast enhancement effect which appeared to be nonlinear and more effective on the images of low incident contrast. However, because of its nonlinear behavior, material parameters should be carefully chosen and optimized to obtain a large contrast improvement. In addition, thick topcoat induced aberration was also taken into account to evaluate the feasibility of the CEL. As a conclusion, it is shown that the CEL is promising for the use of future technologies.