M. Dehan

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFETs with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

Planar Bulk MOSFET s Versus FinFETs: An Analog/RF Perspective

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage, excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them attractive for digital and low-frequency RF applications around 5 GHz, where the performance-power tradeoff is important. On the other hand, in high-frequency applications, planar bulk MOSFETs are seen to hold the advantage over FinFETs due to their higher peak transconductance. However, this comes at a cost of a reduced voltage gain of bulk MOSFETs

Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting trade-off in analog/RF design space. It is seen that FinFETs possess key advantages over bulk FETs for applications around 5 GHz where the performance-power trade-off is important. In case of higher frequency applications bulk MOSFETs are shown to hold the advantage on account of their higher transconductance (Gm), provided a degraded voltage gain and a higher leakage current can be tolerated

Identifying the Bottlenecks to the RF Performance of FinFETs

In this work, the high frequency (RF) performance of FinFETs is investigated in detail using a two-level parasitic model comprising outer and inner parasitic capacitances in addition to parasitic series resistances. Use of scaling relations of these parasitic capacitances with numbers of fins and fingers allows extraction of these elements. Next, by defining a series of reference surfaces, each associated with a certain set of parasitic elements, we proceed to calculate the RF Figures of Merit, namely fT and fmax at these surfaces. These are called ‘available fT (fmax)’ in this work. Analysis of the available fT (fmax) gives insight into the extent to which different parasitics affect the FinFET’s RF performance. The main bottleneck to the FinFET’s RF performance is identified, solutions are proposed and relevant trade-offs are discussed.

Stochastic Matching Properties of FinFETs

For the first time, an experimental assessment of the intradie mismatch properties of a FinFET technology is presented. By applying the analysis to different combinations of gate stack materials, it is shown that the best results are obtained with undoped fins, with matching performances on par or even superior to those of planar MOSFETs. Furthermore, the observation in the narrowest transistors of a noticeable degradation of the mismatch in both the threshold voltage and current factor points to line-edge roughness effects as the presumed key factor influencing intradie mismatch in the smallest fin geometries

VCO design for 60 GHz applications using differential shielded inductors in 0.13 μm CMOS

With the increasing interest in 60 GHz applications, low-cost CMOS circuit solutions emerge. The poor performance of CMOS devices at millimeter-wave frequencies complicates the design. In this work, we present two low-area VCOs covering the license-free 60 GHz band, using differential shielded (slow-wave) transmission line inductors. We discuss design and provide compact modeling of these inductors, compatible with stringent metal density rules of scaled CMOS. Measured phase noise below -90 dBc/Hz at 1 MHz offset is achieved, at a consumption of 3.9 mW at 1 V. The tuning range exceeds 10 %, for a tuning voltage restricted from ground to the supply.

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors

Wafer-level packaging (WLP) technology offers novel opportunities for the realization of high-quality on-chip passives needed in RF front-ends. This paper demonstrates a thin-film WLP technology on top of a 90-nm RF CMOS process with one 15-GHz and two low-power 5-GHz voltage-controlled oscillators (VCOs) using a high-quality WLP or above-IC inductor. The 5-GHz VCOs have a power consumption of 0.33 mW and a phase noise of -115 dBc/Hz and -111 dBc/Hz at 1-MHz offset, respectively, and the 15-GHz VCO has a phase noise of -105 dBc/Hz at 1-MHz offset with a power consumption of 2.76 mW.

Matching Performance of FinFET Devices With Fin Widths Down to 10 nm

In this letter, the matching performances of FinFET devices with high-k dielectric, metal gates, and fin widths down to 10 nm are experimentally analyzed. The stochastic variation of threshold voltage and current factor is examined for both p- and n-type FinFETs. An improvement of the matching performance is expected compared to conventional planar bulk devices since the fins are undoped. The impact of line edge roughness and charge density in the high-k dielectric is evaluated in order to understand which physical parameter fluctuation is dominant on the measured matching parameters.

Suitability of FinFET technology for low-power mixed-signal applications

Wireless applications require a low power technology that enables digital/analog/RF functions on the same chip. FinFET technology presents a competitive alternative to planar CMOS as it features good digital, analog and low-frequency noise performances. Also, very good matching performance is presented here for the first time. Moreover, FinFETs are shown to be attractive for low-power applications below 10 GHz. The suitability of Fin varactors is evaluated and tradeoffs are given. An inductorless oscillator with large tuning range (1-8.5 GHz) for low-power wideband applications is demonstrated for the first time