Srinivasan Venkatraman

A 90nm CMOS single-chip GPS receiver with 5dBm out-of-band IIP3 2.0dB NF

A single-chip GPS receiver with a low-IF heterodyne RF front-end includes a LNA, image-reject IQ mixers, a passive poly-phase filter, and a fully integrated synthesizer. The IF-strip consists of a jammer-reject filter, a VGA, a /spl Delta//spl Sigma/ ADC, and a digital IF-filter. The receiver dissipates 60 mA at 1.4 V and achieves a NF of 2 dB and out-of-band IIP3 of 5 dBm.

An analog front-end signal processor for a 64 Mb/s PRML hard-disk drive channel

Synchronous channel designs, such as partial response maximum likelihood (PRML), are viable for high areal density on a hard-disk drive (HDD). Previously-published PRML channels include a 56 Mb/s channel design but without an on-chip programmable filter, synthesizer or servo demodulator. This 5V BiCMOS integrated circuit contains all the analog front-end functions necessary for a 64Mb/s HDD channel using a rate-8/9 code.<<ETX>>

An analog front-end signal processor for a 64 Mbits/s PRML hard-disk drive channel

This BiCMOS IC contains all the analog front-end components necessary for the design of a 21-64 Mb/s HDD channel. Major functional blocks include an automatic gain control circuit having both analog and digital modes of operation, a programmable filter with 6-33 MHz bandwidth range, two phase-locked loops with 24-72 MHz center frequency ranges, a differential 6 bit flash A/D converter with 24-72 MHz sampling rates, and a write precompensator having 600 ps step size. >

A new tuning scheme for continuous time filters

A new tuning loop is presented for tuning continuous time filters. This tuning loop is applicable mainly to all MOS circuits, in which the tuning range of the filter is severely restricted. It is shown that the tuning loop helps in operating the filter at the desired power efficiency levels, and also extends the tuning range of the filter.

A low power video frequency continuous time filter

A second order Gm-C filter designed in 1 /spl mu/m MOS technology is presented. The main characteristics of the filter are high linearity and low power operation at 5 V supply. This circuit uses MOS gate capacitance for the filter. Circuit performance shows a THD of 55 dB for 1 volt (pk-pk differential) at 1 MHz. The area of the filter is 320 sq. mils. and its power dissipation is 18 mW.