Abhishek Choudhury

Highly-reliable, 30µm pitch copper interconnects using nano-ACF/NCF

Flip chip packaging of ultra fine pitch integrated circuits (ICs) on organic substrates aggravates the stress-strain concerns, requiring a fundamentally different system approach to interconnections, underfill, interfaces, and the substrate. This work demonstrates a novel interconnection solution with excellent reliability for ultra-fine pitch (∼30µm) silicon (Si) on organic first level interconnections by using copper (Cu) pillar with nano-anisotropic conductive film (nano-ACF)/non conductive Film (NCF).

Low temperature, low profile, ultra-fine pitch copper-to-copper chip-last embedded-active interconnection technology

In a continuous drive to achieve low form-factor packages, chip-to-package interconnections have evolved from the conventional solders to a more hybrid technology consisting of copper and solder. However, scaling down the bump pitch to increase the interconnect density poses serious reliability and yield issues. In the previous, a low-profile interconnect architecture, ~20µm total height, was demonstrated comprising of copper-to-copper interconnection and novel adhesive materials. This paper focuses on: (1) design and fabrication of test vehicles to assess the robustness of the interconnect architecture, (2) assembly process development for copper-to-copper interconnections, and (3) reliability and failure analysis of the interconnection. Excellent reliability results are demonstrated under thermal cycling test (TCT) using non-conductive films (NCF) as adhesive. This interconnect scheme is also shown to perform well with different die sizes, die thicknesses and with embedded dies thus offering a great potential for integration with flip chip packages as well as with chip-last embedded active chips in organic substrates. A simple and reliable low-cost and low-temperature direct Cu-Cu bonding is thus demonstrated for the first time.

Multichip Embedding Technology Using Fine-Pitch Cu–Cu Interconnections

Increasing performance and functional density while maintaining low cost is a catalyst for technological progress in the field of packaging. From flip-chip with solder to a hybrid approach of copper and solder, many methods have been created to reach this objective. The 3-D Packaging Research Center at Georgia Tech has been revolutionizing interconnection technology with the multichip embedding chip-last approach, which utilizes ultrathin adhesive-bonded copper bumps to enable ultrafine-pitch chip-to-package interconnections. This technology has been proven to be highly reliable using a low-cost low-temperature direct copper-to-copper bonding approach at 30-μm pitch and ~20-μm standoff height copper-to-copper interconnections. This interconnection method provides a platform for integration with flip-chip packages through its proven ability to work well with different die sizes and thicknesses bonded to the surface of ultrathin organic substrates. The next step in advancing the chip-last approach is to investigate chip embedding at the single-chip and multichip levels. Consequently, this paper focuses on: 1) the design and fabrication of the test vehicle to examine the reliability of the previously demonstrated copper-to-copper interconnections after embedding a thin die in an organic substrate, and 2) assembly process development and reliability data for the interconnections. Specifically, advances in the assembly process include: 1) a novel method to perform chip-last assembly at the panel level leading to a 10-15 times reduction in assembly time per die, and 2) an improved two-step assembly process to achieve simultaneous die embedding and cavity planarization. This embedding technology and its advancements not only allow actives to be embedded in organic substrates but also enables higher functional integration at high-throughput, making chip-last adhesive bonding with low-profile copper-to-copper interconnections a robust chip embedding solution for the next generation of highly integrated heterogeneous subsystems.

Highly Reliable and Manufacturable Ultrafine Pitch Cu–Cu Interconnections for Chip-Last Embedding With Chip-First Benefits

Flip-chip packaging of Ultrafine pitch integrated circuits aggravates the stress-strain concerns as the interconnection pitch is decreased, requiring a fundamentally different system approach to interconnections, underfill processes and interfaces, and the substrate. This paper demonstrates an innovative and manufacturable solution to achieve excellent reliability at Ultrafine pitch (~30 μm) using direct copper-copper (Cu-Cu) interconnections with adhesives. A number of 30-μm bump pitch test vehicles (TVs) were designed with 3 mm × 3 mm chips to extract both daisy chain resistance and single-bump resistance data. Assembled bump resistivity was found to be ~ 3-4× lower than most solders. Performance of these TVs was studied for high temperature storage (HTS) life test, unbiased-highly accelerated stress test (U-HAST) and thermal cycling test (TCT). Test results showed that the assemblies with this next generation interconnection technology depicted excellent reliability results in HTS, U-HAST, and TCT tests. Based on these results, it is concluded that adhesive materials, provide unique opportunities for Ultrafine pitch and high performance interconnections.

Co-electrodeposited graphite and diamond-loaded solder nanocomposites as thermal interface materials

This paper describes a novel co-electrodeposition process to form thin bonding structures based on solder-graphite and solder-diamond nanocomposites for thermal interface materials (TIM). Using this novel processing route, inorganic nanoparticles can be co-plated along with a solder matrix to form unique nanocomposite structures with much enhanced thermal conductivity, engineered thermomechanical properties such as coefficient of thermal expansion (CTE), strength and fatigue resistance, while enabling the benefits of electroplating such as thin film and fine-pitch processing, low-temperature deposition and compatibility with semiconductor and packaging infrastructure. Si-Si and Cu-Cu bonding were demonstrated with these solder nanocomposites having high graphite loading. Pressure-assisted bonding enhanced solder wetting on nanoparticles and improved the bonding characteristics.

Co-W as an advanced barrier for intermetallics and electromigration in fine-pitch flipchip interconnections

The trend towards thinner packages with embedded active components in case of RF modules, and higher I/O densities in case of multicore processors or 3D ICs, are pushing interconnection technologies to its fundamental limits. The limitations of traditional solder bump technologies in terms of its fatigue resistance, current-handling, electromigration and thermomigration resistance has shifted the interconnection focus to advanced thick copper bump UBMs with solder caps. However, even these interconnections fail to meet thermo-mechanical and electrical reliability requirements for fine-pitch flipchip interconnections at high current densities where electromigration becomes a major concern. This paper explores Co-W as an advanced barrier between copper bump and solder cap for fine-pitch flipchip technology to improve electromigration resistance. By suppressing the intermetallic growth and controlling electromigration, the novel barrier is expected to enhance the current-handling and thermomechanical reliability. In a systematic experimental study, Cu-Sn diffusion and intermetallic growth rate of this new Cu-Co-W-Sn-Ag approach are compared with that of Cu-Sn-Ag with XPS depth-profiling and cross-section analysis using SEM and EDS. Based on the analysis, the benefits of Co-W as a solder barrier for fine-pitch flipchip interconnections at high current densities is presented