Dennis Lin

Germanium surface passivation and atomic layer deposition of high-k dielectrics?a tutorial review on Ge-based MOS capacitors

Due to its high intrinsic mobility, germanium (Ge) is a promising candidate as a channel material (offering a mobility gain of approximately??2 for electrons and??4 for holes when compared to conventional Si channels). However, many issues still need to be addressed before Ge can be implemented in high-performance field-effect-transistor (FET) devices. One of the key issues is to provide a high-quality interfacial layer, which does not lead to substantial drive current degradation in both low equivalent oxide thickness and short channel regime. In recent years, a wide range of materials and processes have been investigated to obtain proper interfacial properties, including different methods for Ge surface passivation, various high-k dielectrics and metal gate materials and deposition methods, and different post-deposition annealing treatments. It is observed that each process step can significantly affect the overall metal?oxide?semiconductor (MOS)-FET device performance. In this review, we describe and compare combinations of the most commonly used Ge surface passivation methods (e.g. epi-Si passivation, surface oxidation and/or nitridation, and S-passivation) with various high-k dielectrics. In particular, plasma-based processes for surface passivation in combination with plasma-enhanced atomic layer deposition for high-k depositions are shown to result in high-quality MOS structures. To further improve properties, the gate stack can be annealed after deposition. The effects of annealing temperature and ambient on the electrical properties of the MOS structure are also discussed.

Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution

To address the integration of the high-mobility Ge/III-V MOSFET, a common gate stack (CGS) solution is proposed for the first time and demonstrated on Ge and InGaAs channels with combined hole and electron field-effect mobility values up to 400cm2/eV-s and 1300cm2/eV-s. Based on the duality found on the InGaAs/Ge MOS system, this approach aims to integrate the InGaAs/Ge MOSFET processes for high performance CMOS applications with an emphasis on progressive EOT scaling.

Border Traps in Ge/III–V Channel Devices: Analysis and Reliability Aspects

The aim of this review paper is to describe the impact of so-called border traps (BTs) in high- k gate oxides on the operation and reliability of high-mobility channel transistors. First, a brief summary of the physics of BTs will be given, describing the charge trapping and release in terms of the elastic tunneling model. It will be also pointed out how information on the BT properties can be extracted from popular measurement techniques such as low-frequency (1/f) noise and variable-frequency charge pumping. In the next two parts, the impact of BTs on metal-oxide-semiconductor structures fabricated on Ge or III-V channel materials is outlined, with particular emphasis on the development of novel or adapted measurement techniques such as AC transconductance dispersion or trap spectroscopy by charge injection and sensing. Finally, the effect of BTs on the operation and reliability of high-mobility channel MOSFETs is discussed. It is also shown that the density of BTs is closely linked to the quality or defectivity of the high- k gate stack, indicating room for improvement by optimization of processing or by implementation of a suitable bulk-oxide defect passivation step.

Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs

High-Mobility n-MOSFET options with Ge and InGaAs channels are of intense interests. As the well-known interfacial trap (Dit) problem appears now contained, new challenges are emerging from above the interface. The evidence of oxide border traps (BT) in high-k dielectrics and its effect on the on-state performance of Ge and InGaAs n-MOSFETs are presented in this study through combined trap and transport analyses. The impact of the oxide traps on device frequency response and threshold voltage (Vth) stability could challenge the commercial realization of the high mobility channel MOSFET.

AC Transconductance Dispersion (ACGD): A Method to Profile Oxide Traps in MOSFETs Without Body Contact

We introduce an ac transconductance dispersion method (ACGD) to profile the oxide traps in an MOSFET without needing a body contact. The method extracts the spatial distribution of oxide traps from the frequency dependence of transconductance, which is attributed to charge trapping as modulated by an ac gate voltage. The results from this method have been verified by the use of the multifrequency charge pumping (MFCP) technique. In fact, this method complements the MFCP technique in terms of the trap depth that each method is capable of probing. We will demonstrate the method with InP passivated InGaAs substrates, along with electrically stressed Si N-MOSFETs.

Impact of interface state trap density on the performance characteristics of different III-V MOSFET architectures

Abstract The effect of interface state trap density, D it , on the current–voltage characteristics of four recently proposed III–V MOSFET architectures: a surface channel device, a flat-band implant-free HEMT-like device with δ -doping below the channel, a buried channel design with δ -doping, and implant-free quantum-well HEMT-like structure with no δ -doping, has been investigated using TCAD simulation tools. We have developed a methodology to include arbitrary energy distributions of interface states into the input simulation decks and analysed their impact on subthreshold characteristics and drive current. The distributions of interface states having high density tails that extend to the conduction band can significantly impact the subthreshold performance in both the surface channel design and the implant-free quantum-well HEMT-like structure with no δ -doping. Furthermore, the same distributions have little or no impact on the performance of both flat-band implant-free and buried channel architectures which operate around the midgap.

Oxide Trapping in the InGaAs–

Trap spectroscopy by charge injection and sensing method was applied to the In_0.53Ga_0.47As-Al₂O₃ system, yielding the spatial and energetic distribution of the traps inside the Al₂O₃ layer. The trap density inside the atomic-layer-deposited (ALD) Al₂O₃ layer was found to be significantly reduced by (NH₄)₂S treatment of the InGaAs surface prior to the Al₂O₃ deposition. Indium concentration inside the Al₂O₃ layer was found to be reduced once the InGaAs surface is (NH₄)₂S treated prior to the Al₂O₃ deposition as measured by time-of-flight secondary ion mass spectroscopy, indicating indium as a possible origin of the oxide traps. The results suggest a new mechanism for the sulfur action at the InGaAs surface, which might be responsible for the transistor performance improvements observed after ( NH₄)₂S passivation. This mechanism involves sulfur as an indium diffusion/segregation barrier stabilizing the InGaAs surface during the ALD Al₂O₃ deposition, lowering the oxide trap density. This, in turn, improves the electron mobility through a reduction in the Coulomb scattering of the carriers due to border traps and improves the device drive current.

\hbox{Al}_{2} \hbox{O}_{3}

Our present understanding of BTI in Si and (Si)Ge based sub 1-nanometer EOT MOSFET devices is reviewed and extended to benchmark other Beyond-Si based devices. We discuss the evolution of NBTI for Si-based pMOS devices as a possible showstopper for further scaling below 1nm EOT. Then we present the BTI reliability framework which was developed for SiGe based MOSFET devices, showing strongly improved BTI reliability, explained by carrier-defect decoupling. Also the important issue of increasing stochastic behavior and time dependent variability is discussed. Based on the presented framework developed for SiGe stacks we benchmark alternative Beyond-Si gate stacks using a metric for carrier-defect decoupling, allowing to screen stacks for acceptable reliability.

System and the Role of Sulfur in Reducing the

We present a detailed theoretical analysis to motivate GeSn for CMOS logic. High quality GeSn films have been obtained on Ge-on-Si using a CVD process. A novel surface passivation scheme is presented to achieve record low trap densities at high-κ/GeSn interface. Using the novel surface passivation method, combined with a low thermal budget device fabrication process, n-channel MOSFETs on GeSn with channel Sn content as high as 8.5% have been demonstrated for the first time.

\hbox{Al}_{2}\hbox{O}_{3}

Abstract In this work, we have systematically studied the frequency dispersion of the capacitance–voltage (C–V) characteristics of In0.53Ga0.47As metal–oxide-semiconductor (MOS) capacitors in accumulation region at various temperatures based on a distributed border traps model. An empirical method to evaluate the frequency and temperature dependent response of the border traps distributed along the depth from the interface into the oxide is established. While the frequency dependent response results from the dependence of the time constant of the border traps on their depths, the temperature dependent response is ascribed to the thermal activated capture cross-section of the border traps due to the phonon-related inelastic capturing process. Consequently, it is revealed that the frequency dispersion behaviors of the accumulation capacitance at different temperatures actually reflect the spatial distribution of the border traps. On this basis, we propose a methodology to extract the border trap distribution in energy and space with emphasis on analyzing the C–V characteristics measured from low to high temperatures in sequence.