Vamsi Putcha

Origins and implications of increased channel hot carrier variability in nFinFETs

Channel hot carrier (CHC) stress is observed to result in higher variability of degradation in deeply-scaled nFinFETs than bias temperature instability (BTI) stress. Potential sources of this increased variation are discussed and the intrinsic time-dependent variability component is extracted using a novel methodology based on matched pairs. It is concluded that in deeply-scaled devices, CHC-induced time-dependent distributions will be bimodal, pertaining to bulk charging and to interface defect generation, respectively. The latter, high-impact mode will control circuit failure fractions at high percentiles.

Smart-array for pipelined BTI characterization

Deeply-scaled transistors fabricated in advanced High-k/Metal Gate (HK/MG) technologies have an intrinsic variability, requiring characterization of a large number of transistors to obtain statistically relevant data. A powerful tool in the form of a Smart-array circuit is designed to serve the BTI characterization needs on an industrial scale, where time plays an important role. The Smart-array circuit is designed such that 700 pMOS and nMOS transistors can be measured using the concept of pipelining. A significant reduction of up to 88.5% in time is demonstrated by establishing a pipeline of 15 pMOS transistors and the Measure-Stress-Measure (MSM) scheme of choice.

Advanced MOSFET variability and reliability characterization array

Time-zero variability, bias temperature instability (BTI) and random telegraph noise (RTN) are issues that both analog and digital designers using scaled CMOS technologies have to face. In order to address them at design time, access to a sufficiently large number of individual devices is required for statistical technology characterization and modeling. In this paper we present a large MOSFET array designed and fabricated in an advanced 28nm technology, containing both nMOS and pMOS devices of different sizes, both single and stacked. Measurement data for time-zero and time-dependent variability are shown and discussed. Large scale transistor arrays are an indispensable tool to accurately capture the statistics of variability and reliability mechanisms in advanced technology nodes.

Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: Demonstration of a suitable gate stack for top and bottom tier nMOS

3D Sequential integration has been envisioned to stack transistors in the same front-end process. A crucial challenge is the management of the thermal budget. This work focuses on Si nMOS gate stack challenges, specifically: for a top tier device, by inserting a thin LaSiOx interlayer between SiO2 and HfO2 a sufficient PBTI reliability is demonstrated without resorting to unsuitable high temperature anneals. This gate stack also offers good thermal stability for a pMOS over nMOS scenario.

A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability

Abstract A paradigm for MOSFET instabilities is outlined based on gate oxide traps and the detailed understanding of their properties. A model with trap energy levels in the gate dielectric and their misalignment with the channel Fermi level is described, offering the most successful strategy to reduce both Positive and Negative Bias Temperature Instability (PBTI and NBTI) in a range of gate stacks. Trap temporal properties are determined by tunneling between the carrier reservoir and the trap itself, as well as thermal barriers related to atomic reconfiguration. Trap electrostatic impact depends on the gate voltage and its spatial position, randomized by variations in the channel potential. All internal properties of traps are distributed, resulting in distributions of the externally observable trap parameters, and in turn in time-dependent variability in devices and circuits.

Benchmarking time-dependent variability of junctionless nanowire FETs

Time-dependent variability of junctionless gate-all-around nanowire pFETs is studied through measurements and simulations. The variability, related to effects such as Random Telegraph Noise (RTN) and Bias Temperature Instability (BTI), is discussed in terms of the distribution of individual charged gate oxide trap threshold voltage shifts. This distribution is shown to be shaped by i) the electrostatics of the device, and ii) percolative source-drain conduction. It is concluded that the time dependent variability of our JL GAA NW pFETs is comparable to previously measured pFinFETs. However, provided that other sources of variability are suppressed, JL FETs time-zero and time-dependent variability may remain high due to the high body doping.

BTI reliability of InGaAs nMOS gate-stack: On the impact of shallow and deep defect bands on the operating voltage range of III-V technology

In this work, we show that the reliability of InGaAs channel MOS devices not only depends on density of shallow defect states (i.e., electron traps responsible for PBTI in Si devices), but it is also governed by the density of deep defect states. This limits the operating range of the device. We conclude that it is necessary to characterize both shallow and deep defect densities in order to determine the total operating window (i.e., maximum underdrive and overdrive) of III-V devices for future technologies. We also show that a gate-stack comprising of a new ASM interface layer (ASM-IL), a LaSiOx interlayer and high-k dielectric can achieve the required reliability targets for a low power technology such as III-V.

On the distribution of oxide defect levels in Al2O3 and HfO2 high-k dielectrics deposited on InGaAs metal-oxide-semiconductor devices studied by capacitance-voltage hysteresis

In this work, we study oxide defects in various III-V/high-k metal-oxide-semiconductor (MOS) stacks. We show that the choice of a given starting measurement voltage with respect to the MOS flat-band voltage affects the observed capacitance-voltage hysteresis. We discuss how this behavior can be used to study the distribution of oxide defect levels. With the help of comprehensive experimental data, we show that Al2O3 and HfO2 have different hysteresis characteristics related to different oxide defect distributions. In case of an Al2O3/HfO2 bilayer stack with Al2O3 on the channel side (interfacial layer, IL), as the IL thickness reduces from 3 nm to 0 nm, the hysteresis behavior switches from the typical Al2O3 behavior to the one corresponding to HfO2. We link the characteristic behavior of two dielectrics to the defect level distributions inside their respective band-gaps through a simple energy-driven charging model. Based on the experimental data and simulation results, we show that Al2O3, despite having...

First demonstration of ∼3500 cm 2 /V-s electron mobility and sufficient BTI reliability (max V ov up to 0.6V) In 0.53 Ga 0.47 As nFET using an IL/LaSiO x /HfO 2 gate stack

In this paper, we demonstrate for the first time an implant free In<inf>0.53</inf>Ga<inf>0.47</inf>As n-MOSFET that meets the reliability target for advanced technology nodes with a max operating V<inf>ov</inf> of 0.6 V. In addition, an excellent electron mobility (μ<inf>eff, peak</inf>=3531 cm2/V-s), low SS<inf>lin</inf>=71 mV/dec and an EOT of 1.15 nm were obtained. We also report the scaling potential of this stack to 1nm EOT without loss of performance, reliability and further reduction of the sub-threshold swing (SS<inf>lin</inf>=68mV/dec). On top of the novel IL we presented last year, in this paper we insert a LaSiO<inf>x</inf> layer between the IL and HfO<inf>2</inf> offering an increased chemical stability of the gate stack. This combination is key and offers both an improved interface quality as well as a reduction of the oxide trap density.

BTI reliability and time-dependent variability of stacked gate-all-around Si nanowire transistors

We report experimental results of the N/PBTl (Negative/Positive Bias Temperature Instability) reliability of vertically stacked Gate-All-Around (GAA) silicon nanowire (NW) MOSFETs. We benchmark the lifetime of these novel devices against FinFETs with different widths and similar gate-stack. We do not only compare the average degradation, but also the time-dependent variability. At last, we predict the impact of the nanowire diameter on the reliability using TCAD simulations. Both the experimental results and the simulations indicate that BTI reliability is not negatively impacted down to a nanowire diameter of 6nm.