Adam Cywar

The impact of heater-recess and load matching in phase change memory mushroom cells

Two-dimensional finite element simulations with rotational symmetry are used to analyze the impact of the bottom electrode recess on the reset operation of phase change memory elements with mushroom cell geometry (Ge2Sb2Te5 (GST) film over a patterned TiN pillar). Temperature dependent materials parameters are used for GST and TiN, and the latent heat of fusion in melting of GST is included to model melting. The results of this study indicate that a lower reset current and a more favorable thermal profile may be achieved by extending the active region of GST down into the pillar, due to the heat confinement. It is shown that the current through cells with an insufficient load condition for maximum power transfer can be maintained at a level lower than that which is sufficient for reset operation for extended periods of time due to the non-linear nature of temperature dependent electrical conductivity of GST. These results suggest that if the load condition is not matched, excessive voltage levels or pulse durations would be necessary to achieve successful reset operation across cell arrays.

Melting and crystallization of nanocrystalline silicon microwires through rapid self-heating

Nanocrystalline silicon microwires are self-heated through single, large amplitude, and microsecond voltage pulses. Scanning electron micrographs show very smooth wire surfaces after the voltage pulse compared to as-fabricated nanocrystalline texture. Voltage-pulse induced self-heating leads to significant conductance improvement, suggesting crystallization of the wires. The minimum resistivity during the pulse is extracted from wires of different dimensions as 75.0±4.6 μΩ cm, matching previously reported values for liquid silicon. Hence, nanocrystalline silicon microwires melt through self-heating during the voltage pulse and resolidify upon termination of the pulse, resulting in very smooth and less-resistive crystalline structures.

Phase-change oscillations in silicon microwires

We have observed liquid-solid phase-change oscillations in 2–5.5 μm long silicon wires biased through a load resistor. Molten silicon resistivity is approximately 30 times lower than that of the room temperature solid-state resistivity of the highly doped nanocrystalline-silicon thin film used to fabricate the wires. Wires typically melt with 15–20 V electrical stresses, draining the parasitic capacitance introduced by the experimental setup within 1 μs. The power dissipated in the wire is not sufficient to keep it in molten state after the discharge, leading to repeated melting and resolidification of the wires with 1 MHz, 2–20 mA current oscillations.

Measurements of Liquid Silicon Resistivity on Silicon Microwires

Nanocrystalline silicon microwires are self-heated through microsecond voltage pulses. Nonlinear changes in current level are observed during the voltage pulse, which end with melting

Scaling of Silicon Phase-Change Oscillators

Scalability of silicon-based phase-change oscillators is investigated through experimental and computational studies. These relaxation oscillators are composed of a small volume of silicon, dc biased through a load resistor and a capacitor, which melts due to self-heating and resolidifies upon discharge of the load capacitor. These phase changes lead to high-amplitude current spikes with oscillation frequency that scales with supply voltage, RC time constant, power delivery condition, and heating and cooling rates of the wire. Experimental results are obtained from structures fabricated using silicon-on-insulator substrates. Scaling effects of various parameters are explored using 3-D finite-element simulations coupled with SPICE models.

High temperature electrical resistivity and Seebeck coefficient of Ge2Sb2Te5 thin films

High-temperature characterization of the thermoelectric properties of chalcogenide Ge2Sb2Te5 (GST) is critical for phase change memory devices, which utilize self-heating to quickly switch between amorphous and crystalline states and experience significant thermoelectric effects. In this work, the electrical resistivity and Seebeck coefficient are measured simultaneously as a function of temperature, from room temperature to 600 °C, on 50 nm and 200 nm GST thin films deposited on silicon dioxide. Multiple heating and cooling cycles with increasingly maximum temperature allow temperature-dependent characterization of the material at each crystalline state; this is in contrast to continuous measurements which return the combined effects of the temperature dependence and changes in the material. The results show p-type conduction (S > 0), linear S(T), and a positive Thomson coefficient (dS/dT) up to melting temperature. The results also reveal an interesting linearity between dS/dT and the conduction activat...

Nanosecond Pulse Generation in a Silicon Microwire

We report the generation of trapezoidal current pulses by applying a dc voltage to a single nanocrystalline silicon microwire through a load. The wire is expected to be physically disconnecting and reconnecting at a constriction near its midpoint as a result of volume change in repeated solid-liquid phase transitions. A scanning electron microscope image and the wires electrical characteristics suggest that the wire is partially molten at the time of disconnection. The current pulses rise from 0 to 7 mA and have widths of 13.48 ± 0.65 ns, a repetition rate of 9.12 ± 0.06 MHz, rise/fall times ≤ 350 ps, a peak power density of ~1.9 kW/mm2, and a very consistent pulse shape.

Modeling of Phase-Change Memory: Nucleation, Growth, and Amorphization Dynamics During Set and Reset: Part II—Discrete Grains

We extend our finite-element model of nucleation, growth, and amorphization in phase-change memory devices to model discrete nucleation and grain boundaries, including the evolution of grains within fully crystalline material during long-term anneals. Electrothermal simulations of set and reset operations include a heat of crystallization model and an Arrhenius expression modeling thermionic emission at grain boundaries. Our simulations capture cycle-to-cycle variations due to stochastic nucleation and the interplay of crystallization, the formation of percolation paths, and thermal runaway.

Narrow-channel accumulated-body bulk Si MOSFETs with wide-range dynamic threshold voltage tuning

Side-gated bulk Si nMOSFETs with Si3N4 shallow trench isolation (STI) have been previously demonstrated to have significantly reduced off-currents and improved subthreshold characteristics [1, 2]. The improvement is shown to be due to accumulation of the Si body with the holes as the polysilicon side-gate surrounding the body as a guard ring is negatively biased (Fig 1). The threshold voltage (VT) of the narrow channel devices can be dynamically controlled by the side-gate (Fig 2) voltage (Vside) in a wide range [2, 3], mainly due to the increase in the channel energy barrier (Fig. 3) [4]. Here, we report experimental results on narrow bulk Si accumulated body n-channel FETs with SiO2 side-gate dielectric and STI and p-type side-gates (Fig 2). The fabrication is compatible with established front and back end-of-line processes with only an added side-gate formation and side-gate contact step over conventional FET fabrication. 9 nm thermal SiO2 serves as the side-gate dielectric and 3.6 nm thermal SiO2 is used as gate dielectric. Final body doping is estimated to be at 1 x 1017 cm-3 (Boron). Gate, side-gate, source and drain have high n+ doping (~1 x 1020 cm-3).

Activation energy of metastable amorphous Ge2Sb2Te5 from room temperature to melt

Resistivity of metastable amorphous Ge2Sb2Te5 (GST) measured at device level show an exponential decline with temperature matching with the steady-state thin-film resistivity measured at 858 K (melting temperature). This suggests that the free carrier activation mechanisms form a continuum in a large temperature scale (300 K – 858 K) and the metastable amorphous phase can be treated as a super-cooled liquid. The effective activation energy calculated using the resistivity versus temperature data follow a parabolic behavior, with a room temperature value of 333 meV, peaking to ∼377 meV at ∼465 K and reaching zero at ∼930 K, using a reference activation energy of 111 meV (3kBT/2) at melt. Amorphous GST is expected to behave as a p-type semiconductor at Tmelt ∼ 858 K and transitions from the semiconducting-liquid phase to the metallic-liquid phase at ∼ 930 K at equilibrium. The simultaneous Seebeck (S) and resistivity versus temperature measurements of amorphous-fcc mixed-phase GST thin-films show linear S-T trends that meet S = 0 at 0 K, consistent with degenerate semiconductors, and the dS/dT and room temperature activation energy show a linear correlation. The single-crystal fcc is calculated to have dS/dT = 0.153 μV/K2 for an activation energy of zero and a Fermi level 0.16 eV below the valance band edge.