Azer Faraclas

Modeling of Thermoelectric Effects in Phase Change Memory Cells

Thermoelectric effects on phase change memory elements are computationally analyzed through 2-D rotationally symmetric finite-element simulations of reset operation on a Ge2Sb2Te5 (GST) mushroom cell with 10-nm critical dimension. Temperature-dependent material parameters are used to determine the thermoelectric contributions at the junctions (Peltier heat) and within GST (Thomson heat). Thermal boundary resistances at the GST interfaces enhance the Peltier heat contribution. Peak current densities and thermal gradients are in the order of 250 MA/cm2 and 50 K/nm. Overall, thermoelectric effects are shown to introduce significant voltage polarity dependence on the operation dynamics, peak temperatures, thermal gradients, volume of the molten region, energy required, and resistance contrast. Resistance contrasts of ~ 8.8 × 103 were realized with 155 μA for the positive polarity and 245 μA for the negative polarity.

Modeling of Set and Reset Operations of Phase-Change Memory Cells

Phase-change memory elements with 25-nm Ge2Sb2Te5 thickness and 25-nm heater diameter with ±2-nm protrusion/recess of the heater are studied using 2-D finite-element simulations with rotational symmetry. Temperature-dependent material parameters are used to solve current continuity and heat equations self-consistently. Melting is accounted for by including latent heat of fusion in heat capacity at melting temperature. Electrical breakdown is modeled using additional field-dependent conductivity terms to enable set simulations. Analyses on current, voltage, energy, power, and minimum pitch requirements are summarized for reset/set operations with 1-ns/20-ns voltage pulses leading to ~500× difference between the reset and set resistance states.

Electrical Resistivity of Liquid

The electrical resistivity of liquid Ge2Sb2 Te5 (GST) is obtained from dc-voltage measurements performed on thin GST films as well as from device-level microsecond-pulse voltage and current measurements performed on two arrays (thicknesses: 20 ± 2 nm and 50 ± 5 nm) of lithographically defined encapsulated GST nano-/microwires (length: 315 to 675 nm; width: 60 to 420 nm) with metal contacts. The thin-film measurements yield 1.26 ±0.15 mΩ·cm (thicknesses: 50, 100, and 200 nm); however, there is significant uncertainty regarding the integrity of the film in liquid state. The device-level measurements utilize the melting of the encapsulated structures by a single voltage pulse while monitoring the current through the wire. The melting is verified by the stabilization of the current during the pulse. The resistivity of liquid GST is extracted as 0.31 ± 0.04 and 0.21 ±0.03 mΩ·cm from 20- and 50-nm-thick wire arrays.

\hbox{Ge}_{2} \hbox{Sb}_{2}\hbox{Te}_{5}

A detailed physical model of the heating and amorphization profiles in phase-change memory elements is applied to illustrate the effects of loads and pulse rise times on the reset operation of phase-change memory cells. Finite element modeling of the electrical and thermal transport is used for a mushroom phase-change memory element -- including temperature dependent materials parameters, thermoelectric terms and thermal boundary resistance between different materials - and integrated idealized circuit models are used for the access devices (MOSFET and diode, with a separate series resistance). The results show certain windows of loads and transient times that lead to successful reset operation without excessive wasted power, for the particular PCM cells and programming conditions simulated.

Based on Thin-Film and Nanoscale Device Measurements

Phase change memory is a non-volatile memory technology that utilizes the electrical resistivity contrast between resistive amorphous and conductive crystalline phases of phase change materials. These devices operate at high current densities and high temperature gradients which lead to significant thermoelectric effects. We have performed numerical modeling of electrothermal effects in p-type Ge2Sb2Te5 phase change memory structures suspended on TiN contact pads using COMSOL Multiphysics. Temperature dependent material parameters are used in the model. Strong asymmetry is observed in temperature profiles in all cases: the hottest spot appears closer to the higher potential end suggesting that the thermal profile can be significantly altered by the thermoelectric effects during device operation. Hence, thermoelectric effects need to be considered for device designs for lower power and higher reliability devices.

Operation Dynamics in Phase-Change Memory Cells and the Role of Access Devices

The potential of rupture-oxide mushroom phase-change memory cells is assessed through 2-D finite element analysis using electro-thermal models with temperature-dependent material parameters, coupled with a circuit model for access transistors. The mushroom cell structure used for the simulations consists of a 100-nm thick Ge2Sb2Te5 layer separated from a 20-nm wide TiN bottom heater by a 3-nm thick SiO2 rupture-oxide layer. The ruptured oxide is modeled as a conductive filament through the oxide layer at the center of the heater. The effects of supply voltage, gate voltage, access transistor width, filament diameter and resistivity are studied using a read/reset/read sequence enabled by a dynamic amorphization model. The simulation results show that rupture-oxide cells can be operated with smaller voltages, currents and transistor widths compared to their conventional counterparts for the same resistance contrast. Moreover, it is shown that the cell performance is further improved for narrower and more resistive filaments.

Numerical Modeling of Thermoelectric Thomson Effect in Phase Change Memory Bridge Structures

Phase change memory (PCM) is a possible competitor for future generation non-volatile storage class memory due to its fast writing speed and aggressively scaled packing density. In PCM cells current is confined through narrow conductive paths to create high current densities in a chalcogenide material (Ge2Sb2Te5 or GST is most commonly used). The resulting heat allows the material to switch between crystalline (set) and amorphous (reset) states, changing the cells resistance by ~10-104 times depending on the cell dimensions. Less energy is required for melting smaller regions, therefore aggressive cell scaling results in reduced power and increased packing density. The properties of GST change by orders of magnitude as a function of temperature, and thus understanding its thermal dependency is crucial to accurately model phase change memory cell operation.

Computational Analysis of Rupture-Oxide Phase-Change Memory Cells

Side-gated bulk Si nMOSFETs with Si3N4 shallow trench isolation (STI) have been previously demonstrated to have significantly reduced off-currents and improved subthreshold characteristics [1, 2]. The improvement is shown to be due to accumulation of the Si body with the holes as the polysilicon side-gate surrounding the body as a guard ring is negatively biased (Fig 1). The threshold voltage (VT) of the narrow channel devices can be dynamically controlled by the side-gate (Fig 2) voltage (Vside) in a wide range [2, 3], mainly due to the increase in the channel energy barrier (Fig. 3) [4]. Here, we report experimental results on narrow bulk Si accumulated body n-channel FETs with SiO2 side-gate dielectric and STI and p-type side-gates (Fig 2). The fabrication is compatible with established front and back end-of-line processes with only an added side-gate formation and side-gate contact step over conventional FET fabrication. 9 nm thermal SiO2 serves as the side-gate dielectric and 3.6 nm thermal SiO2 is used as gate dielectric. Final body doping is estimated to be at 1 x 1017 cm-3 (Boron). Gate, side-gate, source and drain have high n+ doping (~1 x 1020 cm-3).

Comparison of instantaneous crystallization and metastable models in phase change memory cells

Phase change memory (PCM) is considered to be a promising candidate for high density, fast and non-volatile memory technologies. PCM devices are resistive memory elements where the crystalline (set) and amorphous (reset) states typically have ∼102–104 times difference in resistance values. The transitions between these states are achieved through localized self-heating with large current densities. Scaling device dimensions improves packing density and speed and results in reduced peak current, power and total energy required for switching [1].

Narrow-channel accumulated-body bulk Si MOSFETs with wide-range dynamic threshold voltage tuning

The authors previously reported wide-range threshold voltage (VT) control and improvement in subthreshold slope (SS) and drain induced barrier lowering (DIBL) in narrow bulk Si Accumulated Body MOSFETs [1-3]. The side-gate structure surrounding the MOSFET body is used for accumulating the body through an independent contact to provide these effects (Fig. 1). In this work, we present a study on the electrostatic body control attained by the side-gates, using experimental and simulated devices.