Ali Gokirmak

Modeling of Thermoelectric Effects in Phase Change Memory Cells

Thermoelectric effects on phase change memory elements are computationally analyzed through 2-D rotationally symmetric finite-element simulations of reset operation on a Ge2Sb2Te5 (GST) mushroom cell with 10-nm critical dimension. Temperature-dependent material parameters are used to determine the thermoelectric contributions at the junctions (Peltier heat) and within GST (Thomson heat). Thermal boundary resistances at the GST interfaces enhance the Peltier heat contribution. Peak current densities and thermal gradients are in the order of 250 MA/cm2 and 50 K/nm. Overall, thermoelectric effects are shown to introduce significant voltage polarity dependence on the operation dynamics, peak temperatures, thermal gradients, volume of the molten region, energy required, and resistance contrast. Resistance contrasts of ~ 8.8 × 103 were realized with 155 μA for the positive polarity and 245 μA for the negative polarity.

Modeling of Set and Reset Operations of Phase-Change Memory Cells

Phase-change memory elements with 25-nm Ge2Sb2Te5 thickness and 25-nm heater diameter with ±2-nm protrusion/recess of the heater are studied using 2-D finite-element simulations with rotational symmetry. Temperature-dependent material parameters are used to solve current continuity and heat equations self-consistently. Melting is accounted for by including latent heat of fusion in heat capacity at melting temperature. Electrical breakdown is modeled using additional field-dependent conductivity terms to enable set simulations. Analyses on current, voltage, energy, power, and minimum pitch requirements are summarized for reset/set operations with 1-ns/20-ns voltage pulses leading to ~500× difference between the reset and set resistance states.

High-temperature thermoelectric transport at small scales: Thermal generation, transport and recombination of minority carriers

Thermoelectric transport in semiconductors is usually considered under small thermal gradients and when it is dominated by the role of the majority carriers. Not much is known about effects that arise under the large thermal gradients that can be established in high-temperature, small-scale electronic devices. Here, we report a surprisingly large asymmetry in self-heating of symmetric highly doped silicon microwires with the hottest region shifted along the direction of minority carrier flow. We show that at sufficiently high temperatures and strong thermal gradients (~1 K/nm), energy transport by generation, transport and recombination of minority carriers along these structures becomes very significant and overcomes convective energy transport by majority carriers in the opposite direction. These results are important for high-temperature nanoelectronics such as emerging phase-change memory devices which also employ highly doped semiconducting materials and in which local temperatures reach ~1000 K and thermal gradients reach ~10–100 K/nm.

Melting and crystallization of nanocrystalline silicon microwires through rapid self-heating

Nanocrystalline silicon microwires are self-heated through single, large amplitude, and microsecond voltage pulses. Scanning electron micrographs show very smooth wire surfaces after the voltage pulse compared to as-fabricated nanocrystalline texture. Voltage-pulse induced self-heating leads to significant conductance improvement, suggesting crystallization of the wires. The minimum resistivity during the pulse is extracted from wires of different dimensions as 75.0±4.6 μΩ cm, matching previously reported values for liquid silicon. Hence, nanocrystalline silicon microwires melt through self-heating during the voltage pulse and resolidify upon termination of the pulse, resulting in very smooth and less-resistive crystalline structures.

Electrical Resistivity of Liquid

The electrical resistivity of liquid Ge2Sb2 Te5 (GST) is obtained from dc-voltage measurements performed on thin GST films as well as from device-level microsecond-pulse voltage and current measurements performed on two arrays (thicknesses: 20 ± 2 nm and 50 ± 5 nm) of lithographically defined encapsulated GST nano-/microwires (length: 315 to 675 nm; width: 60 to 420 nm) with metal contacts. The thin-film measurements yield 1.26 ±0.15 mΩ·cm (thicknesses: 50, 100, and 200 nm); however, there is significant uncertainty regarding the integrity of the film in liquid state. The device-level measurements utilize the melting of the encapsulated structures by a single voltage pulse while monitoring the current through the wire. The melting is verified by the stabilization of the current during the pulse. The resistivity of liquid GST is extracted as 0.31 ± 0.04 and 0.21 ±0.03 mΩ·cm from 20- and 50-nm-thick wire arrays.

\hbox{Ge}_{2} \hbox{Sb}_{2}\hbox{Te}_{5}

We have observed liquid-solid phase-change oscillations in 2–5.5 μm long silicon wires biased through a load resistor. Molten silicon resistivity is approximately 30 times lower than that of the room temperature solid-state resistivity of the highly doped nanocrystalline-silicon thin film used to fabricate the wires. Wires typically melt with 15–20 V electrical stresses, draining the parasitic capacitance introduced by the experimental setup within 1 μs. The power dissipated in the wire is not sufficient to keep it in molten state after the discharge, leading to repeated melting and resolidification of the wires with 1 MHz, 2–20 mA current oscillations.

Based on Thin-Film and Nanoscale Device Measurements

A detailed physical model of the heating and amorphization profiles in phase-change memory elements is applied to illustrate the effects of loads and pulse rise times on the reset operation of phase-change memory cells. Finite element modeling of the electrical and thermal transport is used for a mushroom phase-change memory element -- including temperature dependent materials parameters, thermoelectric terms and thermal boundary resistance between different materials - and integrated idealized circuit models are used for the access devices (MOSFET and diode, with a separate series resistance). The results show certain windows of loads and transient times that lead to successful reset operation without excessive wasted power, for the particular PCM cells and programming conditions simulated.

Phase-change oscillations in silicon microwires

A side-gated ultranarrow channel (width <10nm) silicon field effect transistor (FET) with extreme threshold voltage (Vt) tunability is described. A narrow inversion layer is formed on the top interface controlled by the top gate. The device body and side interfaces are accumulated by up to 1019cm−3 holes, drawn from the substrate by negatively biased side gates (Vside), increasing Vt by 3V, suppressing peripheral leakage currents and short channel effects. Vt response to Vside follows a square root behavior, dVt∕d−Vside=3.73V∕V, similar to that of body doping. Maximum linear tunability (dVt∕dVside) exceeds −2V∕V, average dVt∕dVside is −1.67V∕V.

Operation Dynamics in Phase-Change Memory Cells and the Role of Access Devices

We have developed an automated setup for simultaneous measurement of Seebeck coefficient S(T) and electrical resistivity ρ(T) of thin film samples from room temperature to ∼650 °C. S and ρ are extracted from current-voltage (I-V) measurements obtained using a semiconductor parameter analyzer and temperature measurements obtained using commercial thermocouples. The slope and the x-axis intercept of the I-V characteristics represent the sample conductance G and the Seebeck voltage, respectively. The measured G(T) can be scaled to ρ(T) by the geometry factor obtained from the room temperature resistivity measurement of the film. The setup uses resistive or inductive heating to control the temperature and temperature gradient on the sample. Inductive heating is achieved with steel plates that surround the test area and a water cooled copper pipe coil underneath that generates an AC magnetic field. The measurements can be performed using resistive heating only or inductive heating only, or a combination of both depending on the desired heating ranges. Inductive heating provides a more uniform heating of the test area, does not require contacts to the sample holder, can be used up to the Curie temperature of the particular magnetic material, and the temperature gradients can be adjusted by the relative positions of the coil and sample. Example results obtained for low doped single-crystal silicon with inductive heating only and with resistive heating only are presented.

Accumulated body ultranarrow channel silicon transistor with extreme threshold voltage tunability

Phase change memory is a non-volatile memory technology that utilizes the electrical resistivity contrast between resistive amorphous and conductive crystalline phases of phase change materials. These devices operate at high current densities and high temperature gradients which lead to significant thermoelectric effects. We have performed numerical modeling of electrothermal effects in p-type Ge2Sb2Te5 phase change memory structures suspended on TiN contact pads using COMSOL Multiphysics. Temperature dependent material parameters are used in the model. Strong asymmetry is observed in temperature profiles in all cases: the hottest spot appears closer to the higher potential end suggesting that the thermal profile can be significantly altered by the thermoelectric effects during device operation. Hence, thermoelectric effects need to be considered for device designs for lower power and higher reliability devices.