Faruk Dirisaglik

Modeling of Thermoelectric Effects in Phase Change Memory Cells

Thermoelectric effects on phase change memory elements are computationally analyzed through 2-D rotationally symmetric finite-element simulations of reset operation on a Ge2Sb2Te5 (GST) mushroom cell with 10-nm critical dimension. Temperature-dependent material parameters are used to determine the thermoelectric contributions at the junctions (Peltier heat) and within GST (Thomson heat). Thermal boundary resistances at the GST interfaces enhance the Peltier heat contribution. Peak current densities and thermal gradients are in the order of 250 MA/cm2 and 50 K/nm. Overall, thermoelectric effects are shown to introduce significant voltage polarity dependence on the operation dynamics, peak temperatures, thermal gradients, volume of the molten region, energy required, and resistance contrast. Resistance contrasts of ~ 8.8 × 103 were realized with 155 μA for the positive polarity and 245 μA for the negative polarity.

Electrical Resistivity of Liquid

The electrical resistivity of liquid Ge2Sb2 Te5 (GST) is obtained from dc-voltage measurements performed on thin GST films as well as from device-level microsecond-pulse voltage and current measurements performed on two arrays (thicknesses: 20 ± 2 nm and 50 ± 5 nm) of lithographically defined encapsulated GST nano-/microwires (length: 315 to 675 nm; width: 60 to 420 nm) with metal contacts. The thin-film measurements yield 1.26 ±0.15 mΩ·cm (thicknesses: 50, 100, and 200 nm); however, there is significant uncertainty regarding the integrity of the film in liquid state. The device-level measurements utilize the melting of the encapsulated structures by a single voltage pulse while monitoring the current through the wire. The melting is verified by the stabilization of the current during the pulse. The resistivity of liquid GST is extracted as 0.31 ± 0.04 and 0.21 ±0.03 mΩ·cm from 20- and 50-nm-thick wire arrays.

\hbox{Ge}_{2} \hbox{Sb}_{2}\hbox{Te}_{5}

A detailed physical model of the heating and amorphization profiles in phase-change memory elements is applied to illustrate the effects of loads and pulse rise times on the reset operation of phase-change memory cells. Finite element modeling of the electrical and thermal transport is used for a mushroom phase-change memory element -- including temperature dependent materials parameters, thermoelectric terms and thermal boundary resistance between different materials - and integrated idealized circuit models are used for the access devices (MOSFET and diode, with a separate series resistance). The results show certain windows of loads and transient times that lead to successful reset operation without excessive wasted power, for the particular PCM cells and programming conditions simulated.

Based on Thin-Film and Nanoscale Device Measurements

Phase change memory is a non-volatile memory technology that utilizes the electrical resistivity contrast between resistive amorphous and conductive crystalline phases of phase change materials. These devices operate at high current densities and high temperature gradients which lead to significant thermoelectric effects. We have performed numerical modeling of electrothermal effects in p-type Ge2Sb2Te5 phase change memory structures suspended on TiN contact pads using COMSOL Multiphysics. Temperature dependent material parameters are used in the model. Strong asymmetry is observed in temperature profiles in all cases: the hottest spot appears closer to the higher potential end suggesting that the thermal profile can be significantly altered by the thermoelectric effects during device operation. Hence, thermoelectric effects need to be considered for device designs for lower power and higher reliability devices.

Operation Dynamics in Phase-Change Memory Cells and the Role of Access Devices

Scalability of silicon-based phase-change oscillators is investigated through experimental and computational studies. These relaxation oscillators are composed of a small volume of silicon, dc biased through a load resistor and a capacitor, which melts due to self-heating and resolidifies upon discharge of the load capacitor. These phase changes lead to high-amplitude current spikes with oscillation frequency that scales with supply voltage, RC time constant, power delivery condition, and heating and cooling rates of the wire. Experimental results are obtained from structures fabricated using silicon-on-insulator substrates. Scaling effects of various parameters are explored using 3-D finite-element simulations coupled with SPICE models.

Numerical Modeling of Thermoelectric Thomson Effect in Phase Change Memory Bridge Structures

Side-gated bulk Si nMOSFETs with Si3N4 shallow trench isolation (STI) have been previously demonstrated to have significantly reduced off-currents and improved subthreshold characteristics [1, 2]. The improvement is shown to be due to accumulation of the Si body with the holes as the polysilicon side-gate surrounding the body as a guard ring is negatively biased (Fig 1). The threshold voltage (VT) of the narrow channel devices can be dynamically controlled by the side-gate (Fig 2) voltage (Vside) in a wide range [2, 3], mainly due to the increase in the channel energy barrier (Fig. 3) [4]. Here, we report experimental results on narrow bulk Si accumulated body n-channel FETs with SiO2 side-gate dielectric and STI and p-type side-gates (Fig 2). The fabrication is compatible with established front and back end-of-line processes with only an added side-gate formation and side-gate contact step over conventional FET fabrication. 9 nm thermal SiO2 serves as the side-gate dielectric and 3.6 nm thermal SiO2 is used as gate dielectric. Final body doping is estimated to be at 1 x 1017 cm-3 (Boron). Gate, side-gate, source and drain have high n+ doping (~1 x 1020 cm-3).

Scaling of Silicon Phase-Change Oscillators

Resistivity of metastable amorphous Ge2Sb2Te5 (GST) measured at device level show an exponential decline with temperature matching with the steady-state thin-film resistivity measured at 858 K (melting temperature). This suggests that the free carrier activation mechanisms form a continuum in a large temperature scale (300 K – 858 K) and the metastable amorphous phase can be treated as a super-cooled liquid. The effective activation energy calculated using the resistivity versus temperature data follow a parabolic behavior, with a room temperature value of 333 meV, peaking to ∼377 meV at ∼465 K and reaching zero at ∼930 K, using a reference activation energy of 111 meV (3kBT/2) at melt. Amorphous GST is expected to behave as a p-type semiconductor at Tmelt ∼ 858 K and transitions from the semiconducting-liquid phase to the metallic-liquid phase at ∼ 930 K at equilibrium. The simultaneous Seebeck (S) and resistivity versus temperature measurements of amorphous-fcc mixed-phase GST thin-films show linear S-T trends that meet S = 0 at 0 K, consistent with degenerate semiconductors, and the dS/dT and room temperature activation energy show a linear correlation. The single-crystal fcc is calculated to have dS/dT = 0.153 μV/K2 for an activation energy of zero and a Fermi level 0.16 eV below the valance band edge.

Narrow-channel accumulated-body bulk Si MOSFETs with wide-range dynamic threshold voltage tuning

Phase change memory (PCM) is a high-speed, scalable, resistive non-volatile memory technology that utilizes melting followed by rapid resolidification and annealing above glass-transition temperature to switch a small volume of phase change material to reversibly switch between conductive crystalline and resistive amorphous phases. PCM offers the potential to fill the gap between dynamic random access memory (DRAM) and flash memory with its density, speed, endurance and non-volatility. This potential can be realized with engineering of materials, devices and the electrical signals used for device operation. However, understanding of PCM is rather complicated compared to conventional solid-state devices due to changing material properties, the high temperatures involved. Furthermore, the critically important metastable materials properties, crystallization dynamics, resistance drift and transport mechanism are not well characterized yet [1]-[8].

Activation energy of metastable amorphous Ge2Sb2Te5 from room temperature to melt

The authors previously reported wide-range threshold voltage (VT) control and improvement in subthreshold slope (SS) and drain induced barrier lowering (DIBL) in narrow bulk Si Accumulated Body MOSFETs [1-3]. The side-gate structure surrounding the MOSFET body is used for accumulating the body through an independent contact to provide these effects (Fig. 1). In this work, we present a study on the electrostatic body control attained by the side-gates, using experimental and simulated devices.

Electrical pump-probe characterization technique for phase change materials

Phase change memory (PCM) is an emerging fast and non-volatile memory technology. PCM devices are based on the resistivity contrast between the amorphous (high resistivity) and crystalline (low resistivity) phases. Amorphization (Reset) is achieved by by a large and short electrical pulse which melts a small volume of material and allows fast cooling. Crystallization (Set) is achieved by heating the amorphized region above the crystallization temperature for a sufficiently long duration [1]. These devices operate at high current densities and high temperature gradients which give rise to significant thermoelectric effects observed as asymmetric heating and amorphization of the structures [2]. These effects have been observed in silicon microwires [3] and p-type SbTe [4], doped SbTe [5] and GST phase-change memory cells [6]. Numerical modeling of PCM devices has been performed using approximated analytical solutions to the electro-thermal equations and constant physical parameters [4][6].