Mustafa B. Akbulut

Electrical Resistivity of Liquid

The electrical resistivity of liquid Ge2Sb2 Te5 (GST) is obtained from dc-voltage measurements performed on thin GST films as well as from device-level microsecond-pulse voltage and current measurements performed on two arrays (thicknesses: 20 ± 2 nm and 50 ± 5 nm) of lithographically defined encapsulated GST nano-/microwires (length: 315 to 675 nm; width: 60 to 420 nm) with metal contacts. The thin-film measurements yield 1.26 ±0.15 mΩ·cm (thicknesses: 50, 100, and 200 nm); however, there is significant uncertainty regarding the integrity of the film in liquid state. The device-level measurements utilize the melting of the encapsulated structures by a single voltage pulse while monitoring the current through the wire. The melting is verified by the stabilization of the current during the pulse. The resistivity of liquid GST is extracted as 0.31 ± 0.04 and 0.21 ±0.03 mΩ·cm from 20- and 50-nm-thick wire arrays.

\hbox{Ge}_{2} \hbox{Sb}_{2}\hbox{Te}_{5}

Scalability of silicon-based phase-change oscillators is investigated through experimental and computational studies. These relaxation oscillators are composed of a small volume of silicon, dc biased through a load resistor and a capacitor, which melts due to self-heating and resolidifies upon discharge of the load capacitor. These phase changes lead to high-amplitude current spikes with oscillation frequency that scales with supply voltage, RC time constant, power delivery condition, and heating and cooling rates of the wire. Experimental results are obtained from structures fabricated using silicon-on-insulator substrates. Scaling effects of various parameters are explored using 3-D finite-element simulations coupled with SPICE models.

Based on Thin-Film and Nanoscale Device Measurements

Asymmetric melting was observed in electrically pulsed n-type (phosphorus) nanocrystalline silicon (nc-Si) wires fabricated lithographically. Scanning electron microscope (SEM) images taken from the pulsed wires showed that melting initiates from the ground terminal end of the wires instead of the center as initially expected. Asymmetry in the temperature profile is caused by heat exchanged between charge carriers and phonons when an electrical current is passed along a temperature gradient. This effect is known as Thomson effect, a thermoelectric heat transfer mechanism. One dimensional (1D) time dependent heat diffusion equation including Thomson heat term was solved to model the temperature profile on our structures. The modeling results show that Thomson effect introduces significant shifts in the temperature distribution. The effect of Thomson heat is modeled for various electrical pulse conditions and wires dimensions. Our results indicate that Thomson effect is significant in small scale electronic devices operating under high current densities. Introduction Heat transfer is a critical mechanism in devices that utilize coupled electrical and thermal effects such as thermoelectric devices and phase change memory devices, as well as in conventional electronics. In thermoelectric coolers an electrical current is passed through the junction between two dissimilar materials. Although the cooling occurs at the junction due to the Peltier effect [1], hotspots originated by the applied current appear on both materials. In these devices the location of the hotspot affects the cooling efficiency of the junction and the Thomson effect can be utilized to improve performance [2]. Programming of phase change memory cells is based on Joule heating due to a short current pulse applied through the cell. Thermal transport during the pulse has to be modeled accurately since it directly affects the programming characteristics of the cell [3]. Furthermore, investigation of heat transport at small scales is crucial to understand hotspots formed in electronic devices and integrated circuits which lead to reliability and performance issues [4]. Thomson effect has been observed before in larger scale silicon structures under high current densities [5, 6]. In order to study the Thomson effect on the temperature distribution of electrically pulsed n-type nc-Si sub-μm wires the 1D time dependent heat diffusion equation is solved numerically including heat conduction along the wires and to the substrate, Joule heat and Thomson heat. Fabrication and SEM characterization of pulsed nanocrystalline Si wires Wires with various lengths (L ~ 1-5.5 μm) and widths (W ~ 200 450 nm) with large contact pads were defined on a 75 nm thick n-type (phosphorus) nc-Si film on SiO2, and etched using reactive ion etching (RIE). The resistivity of the films from which the wires were fabricated is about 3x10 Ω.m as determined by four-point probe measurements. The doping density is on the order of 10 cm as determined by Auger analysis. Underlying SiO2 was partially etched, creating a wire bridge between the electrode pads as shown in Figure 1(a). The large area pads are used to probe the wires, and to apply 1 μs voltage pulse with amplitude Mater. Res. Soc. Symp. Proc. Vol. 1083

Scaling of Silicon Phase-Change Oscillators

Thermal assistance has been shown to significantly reduce the required operation power for spin torque transfer magnetic random access memory (STT-MRAM). Proposed heating methods include modified material stack compositions that result in increased self-heating or external heat sources. In this work we analyze the self-heating process of a standard perpendicular magnetic anisotropy STT-MRAM device through numerical simulations in order to understand the relative contributions of Joule, thermoelectric Peltier and Thomson, and tunneling junction heating. A 2D rotationally symmetric numerical model is used to solve the coupled electro-thermal equations including thermoelectric effects and heat absorbed or released at the tunneling junction. We compare self-heating for different common passivation materials, positive and negative electrical current polarity, and different device thermal anchoring and boundaries resistance configurations. The variations considered are found to result in significant differences in maximum temperatures reached. Average increases of 3 K, 10 K, and 100 K for different passivation materials, positive and negative polarity, and different thermal anchoring configurations, respectively, are observed. The highest temperatures, up to 424 K, are obtained for silicon dioxide as the passivation material, positive polarity, and low thermal anchoring with thermal boundary resistance configurations. Interestingly it is also found that due to the tunneling heat, Peltier effect, device geometry, and numerous interfacial layers around the magnetic tunnel junction (MTJ), most of the heat is dissipated on the lower potential side of the magnetic junction. This asymmetry in heating, which has also been observed experimentally, is important as thermally assisted switching requires heating of the free layer specifically and this will be significantly different for the two polarity operations, set and reset.

Numerical Modeling of Electrothermal Effects in Silicon Nanowires

Accumulated body approach for short- and narrow-channel (10-nm scale) bulk Si MOSFETs is analyzed through 3-D finite-element studies. Accumulation of the side interfaces is achieved by a side-gate structure surrounding the body of the transistor, which leads to the accumulation of the body for narrow structures. A separately controlled top gate is used for transistor action. The simulation results show the suppression of leakage currents by 106 times for no side-interface charges, and by 1010 times for an interface positive fixed charge density of 1012 cm-2. The threshold voltage (VT) can be dynamically increased by over 1 V with the accumulation of the body (Vside = 0 to -3 V) for W × L = 10-nm × 15-nm structures, enabling electrostatic VT control and reliable high-temperature (>600 K) operation. Improvements in subthreshold slope and drain-induced barrier lowering are significant for narrower channel devices.

Analysis of self-heating of thermally assisted spin-transfer torque magnetic random access memory

Side-gated bulk Si nMOSFETs with Si3N4 shallow trench isolation (STI) have been previously demonstrated to have significantly reduced off-currents and improved subthreshold characteristics [1, 2]. The improvement is shown to be due to accumulation of the Si body with the holes as the polysilicon side-gate surrounding the body as a guard ring is negatively biased (Fig 1). The threshold voltage (VT) of the narrow channel devices can be dynamically controlled by the side-gate (Fig 2) voltage (Vside) in a wide range [2, 3], mainly due to the increase in the channel energy barrier (Fig. 3) [4]. Here, we report experimental results on narrow bulk Si accumulated body n-channel FETs with SiO2 side-gate dielectric and STI and p-type side-gates (Fig 2). The fabrication is compatible with established front and back end-of-line processes with only an added side-gate formation and side-gate contact step over conventional FET fabrication. 9 nm thermal SiO2 serves as the side-gate dielectric and 3.6 nm thermal SiO2 is used as gate dielectric. Final body doping is estimated to be at 1 x 1017 cm-3 (Boron). Gate, side-gate, source and drain have high n+ doping (~1 x 1020 cm-3).

Three-Dimensional Computational Analysis of Accumulated Body MOSFETs

Phase change memory (PCM) is a high-speed, scalable, resistive non-volatile memory technology that utilizes melting followed by rapid resolidification and annealing above glass-transition temperature to switch a small volume of phase change material to reversibly switch between conductive crystalline and resistive amorphous phases. PCM offers the potential to fill the gap between dynamic random access memory (DRAM) and flash memory with its density, speed, endurance and non-volatility. This potential can be realized with engineering of materials, devices and the electrical signals used for device operation. However, understanding of PCM is rather complicated compared to conventional solid-state devices due to changing material properties, the high temperatures involved. Furthermore, the critically important metastable materials properties, crystallization dynamics, resistance drift and transport mechanism are not well characterized yet [1]-[8].

Narrow-channel accumulated-body bulk Si MOSFETs with wide-range dynamic threshold voltage tuning

The authors previously reported wide-range threshold voltage (VT) control and improvement in subthreshold slope (SS) and drain induced barrier lowering (DIBL) in narrow bulk Si Accumulated Body MOSFETs [1-3]. The side-gate structure surrounding the MOSFET body is used for accumulating the body through an independent contact to provide these effects (Fig. 1). In this work, we present a study on the electrostatic body control attained by the side-gates, using experimental and simulated devices.

Electrical pump-probe characterization technique for phase change materials

Nanocrystalline silicon (nc-Si) micro-bridges are melted and crystallized through Joule heating by applying high-amplitude short duration voltage pulses. Full crystallization of nc-Si bridges is achieved by adjusting the voltage-pulse amplitude and duration. If the applied pulse cannot deliver enough energy to the bridges, only surface texture modification is observed. On the contrary, if the pulse is not terminated after the entire bridge melts, molten silicon diffuses on to the contact pads and the bridge tapers in the middle. Melting of the bridges can be monitored through current-time (I-t) and voltage-time (V-t) measurements during the electrical stress. Conductance of the bridges is enhanced after the electrical stress.