Józef Kulisz

Logic synthesis for PAL-based CPLD-s based on two-stage decomposition

A PAL-based (PAL - Programmable Array Logic) logic block is the core of a great majority of contemporary CPLD (Complex Programmable Logic Device) circuits. The purpose of the paper is to present a novel method of two-stage decomposition dedicated for PAL-based CPLD-s. The key point of the algorithm lies in sequential search for a decomposition providing feasibility of implementation of the free block in one PAL-based logic block containing a limited number of product terms. The proposed method is an alternative to the classical approach, based on two-level minimisation of separate single-output functions. An original method of determining the row multiplicity of the partition matrix is presented. For this purpose a new concept of graph is proposed - the Row Incompatibility and Complement Graph. An appropriate algorithm of the Row Incompatibility and Complement Graph colouring is presented. On the basis of row multiplicity evaluated for individual partitionings, the partitioning which provides minimisation of the bound block is chosen. Results of the experiments, which are also presented, prove that the proposed method leads to significant reduction of chip area in relation to the classical approach, especially for CPLD structures, that consist of PAL-based blocks containing 2^i (a power of 2) product terms. The proposed method was also compared with decomposition algorithms presented in another works. The results lead to a conclusion, that the proposed two-stage PAL decomposition is especially attractive with respect to the number of logic levels obtained.

A novel method of two-stage decomposition dedicated for PAL-based CPLDs

A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a novel method of two-stage PAL decomposition. The idea of the method consist in sequential search for a decomposition providing feasibility of implementation of the free block in a PAL-based logic block containing a limited number of product terms. The proposed approach is an alternative to the classical method based on two-level minimization of separate single-output functions. Results of experiments, which are also presented, prove that the proposed algorithm leads to significant reduction of chip area in relation to the classical method, especially for CPLD structures consisting of PAL-based logic blocks containing 2/sup i/ (a power of 2) product terms.

An IEC 61131-3-based PLC implemented by means of an FPGA

The paper discusses the design process of a programmable logic controller implemented by means of an FPGA device. The PLC implements on the machine language level a subset of the instruction set defined in the EN 61131-3 norm. Different aspects of instruction list and hardware architecture design are presented, however two aspects are the most important: Central Processing Unit (CPU) and the Arithmetic and Logic Unit (ALU). The ALU can execute 34 operations, which include the basic logic operations, comparators, and the four basic arithmetic operations. The operations can be performed for fixed-point and floating-point numbers. All the operations are implemented fully in hardware, so the solution is fast. The developed PLC is implemented using an FPGA device; however, the HDL models used for synthesis can be easily ported to an ASIC.

Decomposition of multi-output functions for CPLDs

A paper presents decomposition method dedicated for PAL based CPLDs. Non-standard usage of decomposition, that leads to minimization of area in implemented circuit and reduction of used logic blocks in programmable structure is the aim of proposed method. Each decomposition step (bound set selection, graph colouring, column pattern coding, etc) is oriented for implementation in PAL-based structure that characterized by PAL-based logic block. Proposed decomposition method is an extension of classical approach commonly thought to be sufficiently efficient. Experiments that were carried out on typical benchmarks show significant area reduction.

State Machine description oriented towards effective usage of vendor-independent synthesis tools

Abstract The paper concerns the problem of Finite State Machine (FSM) description in Hardware Description Languages (HDL), and effective usage of vendor-independent synthesis tools, including academic software, in synthesis dedicated for Complex Programmable Logic Devices (CPLD-s). The authors propose an alternative method of porting a design from a vendor-independent synthesis tool to a vendor system, for completing the implementation stage. The method utilises a special style of VHDL modelling, so the description is universal and comprehendible to a human. Efficiency of the method was verified by experiments carried out using academic software, and leading commercial tools.

A Method of logic synthesis for Pal-Based CPLD-S, based on Two-Stage decomposition 1

Abstract The paper presents a novel method of logic synthesis dedicated for PAL based CPLD-s. The method is based on two-stage decomposition. The key point of the algorithm lies in sequential search for a decomposition providing feasibility of implementation of the Free Block in one PAL-based logic block containing a limited number of product terms. For this purpose a novel concept of graph is used - the Row Incompatibility and Complement Graph. The method is an alternative to the classical approach based on two-level minimization of separate single-output functions. The paper presents also results of experiments, and a comparison of the proposed algorithm vs. the classical method, and commercial tools.

Synthesis of energy-efficient counters implemented in PLD circuits

The paper presents a comparison of four methods of implementing sequential circuits in Programmable Logic Devices in respect of dissipated power. Objective of the research was to investigate influence of different methods of “disabling” the clock signal on the dynamic power consumed by the circuit. The comparison is carried out using simple counter circuits, i. e. circuits the algorithm of which is described by linear graphs. However, the presented considerations are general, and can be applied to any sequential circuit. Results of simulation tests show that the method based on clock gating is the most efficient one, and it leads to significant reduction of the dissipated dynamic power. The authors also propose a simple modification of global clock network structures, to facilitate clock gating.

A Comparative Analysis of Continuous-and Discrete-Time Field Programmable Analogue Arrays

Abstract The paper presents a comparative analysis of field programmable analog arrays (FPAAs), based on the continuous-time and discrete-time techniques, both using voltage and current mode approach. Discrete-time designs are based on switched-capacitor (Se) or switched-current (SI) technology, continuous-time designs are typically designed using the operational transconductance amplifiers (OTAs). The objective of this paper is to determine, which type of FPAA offers the best performance for a given application. The classification is based on the technique (continuous / discrete) and mode (voltage / current) used. The main performance measures are versatility, applicability, range of programmability, insensitivity to parasitics of programming switches, maximum signal / sampling frequency values, range of programmable parameters, signal swing limitations and quality of characteristics of the configured functions

A PC-based object simulator for supporting PLC software development.

Abstract The paper discusses hardware and software tools used to support Programmable Logic Controller (PLC) program testing and verification. An idea of a PC-based object simulator is presented. The simulator consists of a PC equipped with an appropriate I/O card, and a simulator program running on the PC. The simulator is capable of emulating behavior of real industrial objects. Thus a significant part of software tests can be performed with the use of the simulator, instead of a physical object. This can significantly facilitate, and accelerate development of an application.

The row incompatibility and complement graph - A Novel concept of graph for logic synthesis 1

Abstract The paper presents a new concept of graph - the Row Incompatibility and Complement Graph. The idea was developed as a part of a new decomposition algorithm dedicated for PAL-based CPLD-s. A specific feature of the graph is that it contains two kinds of edges: connecting mutually incompatible nodes, and connecting mutually complementing nodes. The graph can be useful in certain class of optimization problems, in which compatibility of bit patterns in both the true and the complemented form has to be analyzed. Appropriate algorithms for the graph building and coloring are also presented.