E Elbert Bechthum

Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM

In an RF transmitter, the function of the mixer and the DAC can be combined in a single block: the Mixing-DAC. For the generation of multicarrier GSM signals in a basestation, high dynamic linearity is required, i.e. SFDR>;85dBc, at high output signal frequency, i.e. fout ≈ 4GHz. This represents a challenge which cannot be addressed efficiently by current available hardware or state-of-the-art published solutions. Mixing locality indicates if the mixing operation is executed locally in each DAC unit cell or globally on the combined DAC output signal. The mixing locality is identified as one of the most important aspects of the Mixing-DAC architecture with respect to linearity. Simulations of a current steering Mixing-DAC show that local mixing with a local output cascode can result in the highest linearity, i.e. IMD3<;-88dBc at fout=4GHz.

A Wideband RF Mixing-DAC Achieving IMD < -82 dBc Up to 1.9 GHz

This paper presents a highly linear wideband Mixing-DAC architecture. A current-steering DAC core and a mixer are co-integrated at a unit current-cell level. A 1 bit DAC output stage is cascoded by a 1 bit mixer to form the Mixing-DAC current cell. An array of such current cells and a system front-end construct the Mixing-DAC. The system front-end includes digital signal processing and data synchronization, global LO driver and sort-and-combine calibration hardware. To reach high linearity, various techniques are used: digital dither, self measurement and calibration of amplitude and timing errors, local advanced cascoding scheme, bleeding currents, segmentation and accurate scaling of the LSB binary current cells. The proposed approach is validated by a 65 nm CMOS test-chip of a dual 16 bit 2 GS/s 4 GHz Mixing-DAC with IMD <; -82 dBc up to 1.9 GHz and output noise lower than -165 dBm/Hz.

Timing error measurement for highly linear wideband Digital to Analog Converters

The switching characteristics of Digital to Analog Converter (DAC) unit elements can limit DAC dynamic performance at high speeds [1]. Unbalances and mismatches in clock, data and output networks create a non-identical environment for every current cell. Together with mismatch in current cell switching transistors and other non-idealities, this causes the switching characteristics of the current cells to be non-identical. A new method for measuring the timing error is presented. The measurement method is shown to be insensitive to all important non-idealities in the DAC and the measurement circuit. Transistor level simulations show that the measurement accuracy is better than 125fs. Together with an ideal calibration loop, this measurement accuracy can lead to an average SFDR of more than 95dB when applied to an exemplary 12 bit 1GSps DAC.

A novel timing-error based approach for high speed highly linear Mixing-DAC architectures

In current steering Mixing-DACs with local mixing, timing errors between the current cells is a major concern. This paper considers two types of random timing errors: delay and duty-cycle. Analysis shows that the Mixing-DAC is sensitive to delay errors, but much less sensitive to duty-cycle errors. For the required high spectral purity of future 4GHz multicarrier GSM (SFDRRBW=85dBc), the delay spread σ(delay) should be <;36fs. Therefore, only mixing in the output stage with a single LO driver can achieve the desired linearity. The presented analysis shows that the timing of the binary cells in the segmented converter is very important, especially in a back-off scenario. Simulations confirm that accurate capacitance scaling at the high-frequency nodes of the binary current cells is crucial. A new, back-off aware segmentation trade-off is proposed, which shows the impact of the SFDRRBW and backoff requirements on the segmentation choice. The proposed methods result in an optimal Mixing-DAC architecture, implemented in 65nm CMOS, with a simulated performance of SFDRRBW=86dBc at 4GHz output frequency and -16dBFS/tone output power (10dB back-off).

9.6 A 5.3GHz 16b 1.75GS/S wideband RF Mixing-DAC achieving IMD<-82dBc up to 1.9GHz

Cellular multicarrier transmitters for communication infrastructure require both high linearity and large bandwidth (BW) at GHz frequencies. The combination of multicarrier GSM, WCDMA and LTE typically requires IMD<;-80dBc and SFDR>80dBc in a large transmit bandwidth of 300MHz and at an output frequency of up to 3.5GHz and beyond. Current-Steering (CS) Nyquist DACs have large BW, but their linearity drops for increasing output frequencies [1]. A separate mixer is therefore needed to generate an RF signal with high linearity. A Mixing-DAC integrates the function of the mixer and DAC together. Using a Mixing-DAC can result in different architecture trade-offs which potentially enable a reduction of the cost and power consumption, while improving the linearity at high frequencies. The state-of-the-art Mixing-DACs attain linearity by means of A2 modulation [2,3] or low sample rate [4], but this results in a limited BW and does not result in a linearity better than IMD=-71dBc. Even a GaAs implementation [5] only achieves IMD=-70dBc while consuming 1.2W.

A novel output transformer based highly linear RF-DAC architecture

A major limitation of the linearity of Current Steering (CS) RF-DACs is the large output voltage swing (typically 1Vpp), which couples to sensitive internal nodes and thereby causes non-linear distortion. This paper proposes a novel approach for the linearization of the CS RF-DAC. An output transformer decouples the output from the circuit core and attenuates the voltage swing seen by the RF-DAC current cells. A lumped element model of a transformer is used in calculations and simulations to analyze the performance of the transformer in the Mixing-DAC application, and to select optimal design parameters for high linearity. Verification with a simulation model of an RF-DAC shows that the output related non-linearity (IMD3) of the CS RF-DAC improves with about 14dB when the proposed transformer parameters are used.