José Luis Martín

Variable-Frequency Grid-Sequence Detector Based on a Quasi-Ideal Low-Pass Filter Stage and a Phase-Locked Loop

This paper proposes a filtered-sequence phase-locked loop (FSPLL) structure for detection of the positive sequence in three-phase systems. The structure includes the use of the Park transformation and moving average filters (MAF). Performance of the MAF is mathematically analyzed and represented in Bode diagrams. The analysis allows a proper selection of the window width of the optimal filter for its application in the dq transformed variables. The proposed detector structure allows fast detection of the grid voltage positive sequence (within one grid voltage cycle). The MAF eliminates completely any oscillation multiple of the frequency for which it is designed; thus, this algorithm is not affected by the presence of imbalances or harmonics in the electrical grid. Furthermore, the PLL includes a simple-frequency detector that makes frequency adaptive the frequency depending blocks. This guarantees the proper operation of the FSPLL under large frequency changes. The performance of the entire PLL-based detector is verified through simulation and experiment. It shows very good performance under several extreme grid voltage conditions.

Hardware implementation of optical flow constraint equation using FPGAs

This paper describes the hardware implementation of a high complexity algorithm to estimate the optical flow from image sequences in real time. Optical flow estimation from image sequences has been for several years a mathematical process carried out by general purpose processors in no real time. In this work, a specific architecture for this task has been developed and tested with simulators of hardware description languages. This architecture can estimate the optical flow in real time and can be constructed with FPGA or ASIC devices. This hard-ware has many applications in fields like object recognition, image segmentation, autonomous navigation, and security systems. The final system has been developed with hardware that combines FPGA technology and discrete FIFO memories.

Performance Evaluation of Fault-Tolerant Neutral-Point-Clamped Converters

This paper presents a study of the fault tolerance capacity of a neutral-point-clamped converter. Different faults in power semiconductors are considered, and the available postfault states of the converter are shown. In regard of the operation limits, two possible solutions are presented. In these solutions, adding a reduced number of additional components, the behavior of the converter when a switch fails improves considerably. Furthermore, an analysis of the neutral-point voltage balancing conditions after a fault and reconfiguration of the system is also evaluated. Experimental results that prove the correct operation of the proposed topologies are shown.

New Protection Circuit for High-Speed Switching and Start-Up of a Practical Matrix Converter

The matrix converter (MC) presents a promising topology that needs to overcome certain barriers (protection systems, durability, the development of converters for real applications, etc.) in order to gain a foothold in the market. Taking into consideration that the great majority of efforts are being oriented toward control algorithms and modulation, this paper focuses on MC hardware. In order to improve the switching speed of the MC and thus obtain signals with less harmonic distortion, several different insulated-gate bipolar transistor (IGBT) excitation circuits are being studied. Here, the appropriate topology is selected for the MC, and a recommended configuration is selected, which reduces the excursion range of the drivers, optimizes the switching speed of the IGBTs, and presents high immunity to common-mode voltages in the drivers. Inadequate driver control can lead to the destruction of the MC due to its low ride-through capability. Moreover, this converter is especially sensitive during start-up, as, at that moment, there are high overcurrents and overvoltages. With the aim of finding a solution for starting up the MC, a circuit is presented (separate from the control software), which ensures correct sequencing of supplies, thus avoiding a short circuit between input phases. Moreover, it detects overcurrent, connection/disconnection, and converter supply faults. Faults cause the circuit to protect the MC by switching off all the IGBT drivers without latency. All this operability is guaranteed even when the supply falls below the threshold specified by the manufacturers for the correct operation of the circuits. All these features are demonstrated with experimental results. Lastly, an analysis is made of the interaction that takes place during the start-up of the MC between the input filter, clamp circuit, and the converter. A variation of the clamp circuit and start-up strategy is presented, which minimizes the overcurrents that circulate through the converter. For all these reasons, it can be said that the techniques described in this paper substantially improve the MC start-up cycle, representing a step forward toward the development of reliable MCs for real applications.

Frequency-Adaptive Stationary-Reference-Frame Grid Voltage Sequence Detector for Distributed Generation Systems

This paper proposes a stationary-frame sequence detector (SFSD) structure for determining the positive sequence in three-phase systems. The structure includes the use of the Clarke transformation and moving average filters (MAFs). The positive-sequence phase angle can be obtained from the alpha-beta components; however, such a detection becomes inaccurate if the grid voltages are unbalanced and/or distorted. The MAF is used to filter the nonideal components. Performance of the MAF is analyzed mathematically for a proper selection of the window width of the optimal filter in this application. The time delay introduced by MAFs is constant and known; hence, this may be compensated. The proposed detector structure allows fast detection of the grid voltage positive sequence (within one grid voltage cycle). The MAF completely eliminates any oscillation multiple of the frequency for which it is designed; thus, this algorithm can overcome the presence of imbalances or harmonics in the electrical grid. Furthermore, it includes a simple frequency estimator that makes the SFSD frequency adaptive and is capable of operating under large frequency changes. The entire SFSD is verified through simulation and experiment, showing very good performance even under several extreme grid voltage conditions.

Fault-Tolerant Neutral-Point-Clamped Converter Solutions Based on Including a Fourth Resonant Leg

This paper presents a new three-level topology based on the neutral-point (NP)-clamped converter. An additional leg is added to the basic topology. The main purpose of this leg is to provide the converter with fault-tolerant capabilities. In addition, during normal operation mode, the fourth leg can be used to balance the NP voltage. In this way, the low-frequency voltage oscillations that appear in the NP under some operating conditions are cancelled out effectively. As a result, the modulation strategy of the three main legs of the converter does not have to take care of the voltage balance and can focus on other aspects such as, for instance, minimizing the switching losses of the converter. However, the inclusion of the fourth leg produces some additional losses. A resonant topology is proposed to minimize the switching losses of this leg. Three different fault-tolerant solutions based on the fourth-leg topology are presented. A comparison of these topologies showing their respective advantages and drawbacks is made. Experimental results are presented to show the viability of this approach.

A Step Forward Towards the Development of Reliable Matrix Converters

The matrix converter can be used in a wide range of applications. Nevertheless, it does not yet represent a sufficiently mature option for industrialization. In order to resolve this problem, this paper examines the hardware of the matrix converter and identifies all the circuits that should be included in this. It also quantifies the operating conditions and provides practical guidelines for the step-by-step design of a matrix converter. These considerations are validated with experimental results. In this way, it can be said that this paper represents a step forward toward the development of reliable matrix converters for real applications.

Overview of FPGA-Based Multiprocessor Systems

Modern Systems-on-Chip (SoC) development is moving toward multiprocessor-based design. Embedded systems have evolved from an uniprocessor to a multiprocessor approach, seeking better performance and less energy consumption. It is widely accepted that Multiprocessor Systems-on-Chip (MPSoC) will become the predominant class of embedded systems in future. In addition, advances in FPGA technology makes it possible to implement complete multiprocessor systems in a single FPGA. It allows fast design, implementation and testing of new devices. This paper presents an overview of FPGA-based multiprocessor systems. It describes the main characteristics, comments on several FPGA-based multiprocessor systems appearing in the research community in the last 5 years and discusses some of the challenges in this field.

Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications

Abstract Every month new applications of fuzzy logic to image processing appear. The lightly tight nature of fuzzy algorithms simulates human vision and thus, the field of applications widens. This paper implements in hardware a very popular fuzzy algorithm, the Fuzzy C-Means algorithm. The version of the algorithm allows a high degree of parallelism, which makes the hardware implementation suited for real-time video applications.

Hardware architecture for optical flow estimation in real time

Optical flow estimation from image sequences has been for several years a mathematical process carried out by general purpose processors in no real time. A specific architecture for this task has been developed and tested with simulators of hardware description languages. This architecture can estimate the optical flow in real time and can be constructed with FPGA or ASIC devices. This hardware may have many applications in fields like object recognition, image segmentation, autonomous navigation and security systems. To simulate image processing models described in VHDL an application specific test bench has been designed.