Jagoba Arias

Malguki: an RSSI based ad hoc location algorithm

Abstract The problem of finding the location of a node in wireless networks has been a research interest in the last years. In environments where the GPS does not work, the estimation of a node position using only RF signals is not a trivial task. Although some other systems have been proposed so far, using ultrasonic signals, IR, etc. But those require additional hardware that is only to be used for location finding. This article describes an algorithm, which computes the location of a node using noisy distance estimations. Thus, the restriction on distance exactitude can be relaxed and RF signal based distance estimations may be used to estimate the node location.

LL-MAC: A low latency MAC protocol for wireless self-organised networks

This paper proposes LL-MAC, a medium access control (MAC) protocol specifically designed for wireless sensor network applications that require low data latency. Wireless sensor networks use battery-operated computing and sensing devices and their main application is environmental monitoring. In order to achieve such requirements, the whole network must work autonomously and collaborate in periodically sensing the surrounding environment and sending data to the sink. LL-MAC uses novel techniques to offer a low end-to-end data transmission latency from the furthest away nodes to the sink in a unique working cycle while offering a low duty cycle operation in a multi-hop fashion. Key features of this protocol include a synchronised sleep schedule to reduce control overhead along with a mechanism to avoid overhearing unnecessary traffic and elude collisions. Finally, control interval adjustment enables power-aware topology management in changing environments.

Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications

Abstract Every month new applications of fuzzy logic to image processing appear. The lightly tight nature of fuzzy algorithms simulates human vision and thus, the field of applications widens. This paper implements in hardware a very popular fuzzy algorithm, the Fuzzy C-Means algorithm. The version of the algorithm allows a high degree of parallelism, which makes the hardware implementation suited for real-time video applications.

Neuro semantic thresholding using OCR software for high precision OCR applications

This paper describes a novel approach to binarization techniques. It presents a way of obtaining a threshold that depends both on the image and the final application using a semantic description of the histogram and a neural network. The intended applications of this technique are high precision OCR algorithms over a limited number of document types. The input image histogram is smoothed and its derivative is found. Using a polygonal version of the derivative and the smoothed histogram, a new description of the histogram is calculated. Using this description and a training set, a general neural network is capable of obtaining an optimum threshold for our application.

A top-down design for the train communication network

A new electronic design for a TCN (train communication network) bus is presented in this paper. Based on top-down philosophy and focused on system on a chip strategies, various of its modules are expected to be reused in some other designs for complex communication circuits. In order to verify the Class 1 device proposed for MVB (multifunction vehicle bus), its final description has been synthesized. The advantages and problems encountered are described. The process proposed to refine system description is based on these three models: an algorithmic model using a high level language, a functional model in VHDL and the final model for synthesis, also in VHDL. The simulation and verification process has been accounted from the initial algorithmic model, so much time has been saved. Translation between algorithmic and functional models is straightforward because both descriptions have been intentionally made similar, but much care must be taken to take advantage of concurrency in HDL. The last model for synthesis conversion is based on structural division, by making smaller blocks from the functional description. Exhaustive simulation using specific testbenches has validated each model. Although design flow is generic enough to be used in other cases, such a device is a good test for this methodology. Bottom-up design methodology and a multichip approach were used during an initial experience in MVB device synthesis.

SOM Segmentation of gray scale images for optical recognition

This paper describes a clustering technique using Self Organizing Maps and a two-dimensional histogram of the image. The two-dimensional histogram is found using the pixel value and the mean in the neighborhood. This histogram is fed to a self organizing map that divides the histogram into regions. Carefully selecting the number of regions, a scheme that allows an optimum optical recognition of texts can be found.The algorithm is specially suited for optical recognition application where a very high degree of confidence is needed. As an example application, the algorithm has been tested in a voting application, where a high degree of precision is required. Furthermore, the algorithm can be extended to any other thresholding or clustering applications.

Hardware architecture for a general regression neural network coprocessor

This article presents a series of hardware implementations of a general regression neural network (GRNN) using FPGAs. The paper describes the study of this neural network using different fixed and floating point implementations. The implementation includes training as well as testing of the network. It is focused on precision loss and area and speed results of the resulting neural network coprocessor that can be used in a System on Programmable Chip. A GRNN is able to approximate functions and it has been used in control, prediction, fault diagnosis, engine management among others. They are mainly implemented as software entities because they require a great amount of complex mathematical operations. With the increasing power and capabilities of current FPGAs, now it is possible not only to translate them into hardware but, due to the reconfigurable feature of these devices, to explore different hardware/software partitions as well. These hardware implementations increase both the speed and performance of these neural networks and the designer can select the area-speed trade-off that best fits the application.

Comparison of two designs for the multifunction vehicle bus

In this paper, two designs for the decoder of the multifunction vehicle bus (MVB) are compared. The first one follows a bottom-up methodology and the second one has been created in a top-down style. Although this latter methodology is more systematic and easy to automate, it results in a lower performance. In the case of the MVB decoder, the ratio of bottom-up performance to the top-down one ranges from 1.90 to 4.12, depending on the synthesis tool and the device. Selecting as reference the tool and field-programmable gate array (FPGA) that use the fewest logical elements, the bottom-up design can work 2.3 times faster than the top-down one, after two and three iterations for the physical implementation, respectively. In both cases, the circuit has been synthesized on a Virtex-E XCV3200E of Xilinx by Xilinx Synthesis Tool (XST), so that there has been no shortage of physical resources. Therefore, for a particular pair of synthesis tool and device, the final implementation is determined by the design style and not by a hard placement and routing in a hostile fabric. After synthesis, the top-down design was 23.37% larger than the bottom-up design, so the results are not as poor as expected from a nonstructured design; however, this percentage, which is always positive, depends very strongly upon the particular synthesis tool and FPGA. In addition, both descriptions have been completely implemented in a similar CPU time (even the top-down one slightly more quickly, at the first attempt). So the top-down design style is a good candidate to produce circuits in a short time to market (in this case 28% lower), although synthesis tools must be improved in order to increase the performance.

Multiprocessor SoPC-Core for FAT volume computation

Abstract This paper presents the design, co-simulation and implementation of a Soft-core for the autonomous reading of a file stored into IDE devices formatted with FAT16 File Data System. This application illustrates a novel core architecture that embeds multiple customized tiny microprocessors and standard interfaces into the core. The reconfigurable nature of the FPGA implementation allows easy modifications of the microprocessors and peripheral hardware to cover other control applications. Emphasis is placed on presenting how the co-design and co-simulation of the processors, additional hardware, buses and communications has been possible with the developed specific Virtual Environment.

Simulink/Modelsim Simulabel VHDL PID Core for Industrial SoPC Multiaxis Controllers

This paper presents a PID controller core described in VHDL suitable to be introduced into a system-on-programmable chip design. The flexibility of the system-on-a-programmable-chips (SoPCs) in motor multi-axis control systems makes possible the processing of the most intensive computation operations by hardware (PID IP cores) and the trajectory computation by software. Usually the trajectory generation software runs in powerful FPGA embedded microprocessors. The main problem of this approach is the difficulty to tune the VHDL code into the final electrical system. That is why the article also describes the simulation framework needed to validate the model using Simulink. In this way, we can obtain both the high performance of a hardware implementation and the validation and testing capabilities of a Simulink design