Carlos Cuadrado

Hardware implementation of optical flow constraint equation using FPGAs

This paper describes the hardware implementation of a high complexity algorithm to estimate the optical flow from image sequences in real time. Optical flow estimation from image sequences has been for several years a mathematical process carried out by general purpose processors in no real time. In this work, a specific architecture for this task has been developed and tested with simulators of hardware description languages. This architecture can estimate the optical flow in real time and can be constructed with FPGA or ASIC devices. This hard-ware has many applications in fields like object recognition, image segmentation, autonomous navigation, and security systems. The final system has been developed with hardware that combines FPGA technology and discrete FIFO memories.

Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications

Abstract Every month new applications of fuzzy logic to image processing appear. The lightly tight nature of fuzzy algorithms simulates human vision and thus, the field of applications widens. This paper implements in hardware a very popular fuzzy algorithm, the Fuzzy C-Means algorithm. The version of the algorithm allows a high degree of parallelism, which makes the hardware implementation suited for real-time video applications.

Neuro semantic thresholding using OCR software for high precision OCR applications

This paper describes a novel approach to binarization techniques. It presents a way of obtaining a threshold that depends both on the image and the final application using a semantic description of the histogram and a neural network. The intended applications of this technique are high precision OCR algorithms over a limited number of document types. The input image histogram is smoothed and its derivative is found. Using a polygonal version of the derivative and the smoothed histogram, a new description of the histogram is calculated. Using this description and a training set, a general neural network is capable of obtaining an optimum threshold for our application.

A top-down design for the train communication network

A new electronic design for a TCN (train communication network) bus is presented in this paper. Based on top-down philosophy and focused on system on a chip strategies, various of its modules are expected to be reused in some other designs for complex communication circuits. In order to verify the Class 1 device proposed for MVB (multifunction vehicle bus), its final description has been synthesized. The advantages and problems encountered are described. The process proposed to refine system description is based on these three models: an algorithmic model using a high level language, a functional model in VHDL and the final model for synthesis, also in VHDL. The simulation and verification process has been accounted from the initial algorithmic model, so much time has been saved. Translation between algorithmic and functional models is straightforward because both descriptions have been intentionally made similar, but much care must be taken to take advantage of concurrency in HDL. The last model for synthesis conversion is based on structural division, by making smaller blocks from the functional description. Exhaustive simulation using specific testbenches has validated each model. Although design flow is generic enough to be used in other cases, such a device is a good test for this methodology. Bottom-up design methodology and a multichip approach were used during an initial experience in MVB device synthesis.

Real-Time Stereo Vision Processing System in a FPGA

This paper describes a reconfigurable digital architecture to compute dense disparity maps at video-rate for stereo vision. The processor architecture is described in synthetizable VHDL and, by means of the reconfigurability, the hardware requirements are optimized for different image resolutions and matching scenarios. The configurable description of a stereo processor provides the entity to design stereo matching systems, implementing by incremental design multi-baseline or multi-scale stereo vision algorithms. We show the results of the synthesis and its implementation cost in logic elements and time delays. The synthesis results have been implemented in a practical prototype

SOM Segmentation of gray scale images for optical recognition

This paper describes a clustering technique using Self Organizing Maps and a two-dimensional histogram of the image. The two-dimensional histogram is found using the pixel value and the mean in the neighborhood. This histogram is fed to a self organizing map that divides the histogram into regions. Carefully selecting the number of regions, a scheme that allows an optimum optical recognition of texts can be found.The algorithm is specially suited for optical recognition application where a very high degree of confidence is needed. As an example application, the algorithm has been tested in a voting application, where a high degree of precision is required. Furthermore, the algorithm can be extended to any other thresholding or clustering applications.

A TCN Gateway Emulator

TCN standard makes use of the WTB bus and MVB vehicle buses to provide necessary services which a train may require. This architecture takes advantage of complex multiprocessor gateways to link a vehicle bus to the wire train bus. To provide a robust development and verification environment, a TCN gateway emulation application has been created. This program develops a virtual network to test the TCN protocol stack and applications built on top of it.

An emulator to develop the Wire Train Bus protocol stack

Buses in modern trains must cope with dynamic on-board network topologies while ensuring that data are delivered in real time. This is the case of the wire train bus, in which most of the nodes are complex multi-processor gateways. In these systems, the link layer related tasks, as defined in the train communication network (TCN) standard, need all the power of a dedicated processor. However, the development of the firmware is prone to errors and misinterpretations of the text. To provide a robust development and verification environment, a TCN emulation application has been created. This program lets the developer create a virtual network to debug and test the TCN protocol stack and eventually, applications built on top of it

High Throughput Serpent Encryption Implementation

Very high speed and small area hardware architectures of the Serpent encryption algorithm are presented in this paper. The Serpent algorithm was a submission to the National Institute of Technology (NIST) as a proposal for the Advanced Encryption Standard (FIPS-197). Although it was not finally selected, Serpent was considered very secure and with a high potential in hardware implementations. Among others, a fully pipelined Serpent architecture is described in this paper and when implemented in a Virtex-II X2C2000-6 FPGA device, it runs at a throughput of 40 Gbps.

Dependability in FPGAs, a Review

Field Programmable Gate Arrays (FPGAs) are commonly used in safety-critical and mission-critical systems. In these applications failures are unacceptable, since they can lead to people injured or huge economical losses. Due to Moores law and the continuous size reduction, electronic devices are able to perform more and more complex functionalities. However, they are becoming more and more vulnerable to radiation. Single event effects (SEE) are the major reliability concern in FPGAs, which are the effects provoked by radiation particles. Dependability has to be addressed at all stages of the system lifecycle, from design to decommissioning, in order to meet the dependability requirements. Since dependability issues have been observed in electronic systems, several dependability mechanisms have been developed. This work makes a review on the existing mechanisms necessary to obtain a dependable system and divides them in four groups; fault prevention, fault tolerance, fault removal and fault forecasting.