Ajit P. Paranjpe

Single-wafer integrated semiconductor device processing

The authors present an overview of various single-wafer fabrication techniques for integrated processing of microelectronic devices. Numerous processing modules, sensors, and associated fabrication processes have been developed for advanced semiconductor device manufacturing. The combination of single-wafer processing, cluster tools, sensors, and advanced factory control/computer-integrated manufacturing techniques provides a capability for flexible fast-cycle-time device manufacturing. Specific developments and results are described in the areas of dry/vapor-phase surface cleaning, epitaxy, plasma processing, rapid thermal processing, and in situ sensors. An integrated sub-half micrometer CMOS technology based on these single-wafer fabrication methods including rapid thermal processing is also described. >

Fast-cycle-time single-wafer IC manufacturing

Abstract This paper presents a demonstration of the total use of RTP for fast-cycle-time semiconductor IC production. The feasibility of eliminating batch processing for CMOS IC fabrication has been shown. Our fast-cycle-time flexible single-wafer minifactory contains 34 single-wafer processors having various combinations of at least 9 different in-situ process monitoring and control sensors. Forty device fabrication processes are done with these systems, the majority being Advanced Vacuum Processors (AVPs). Multiple combinations of process energy sources and in-situ sensors are used to perform many process steps. Vacuum wafer cassettes are used for transporting wafers in a clean environment between machines. All of the AVPs are driven and supervised by a computer-integrated manufacturing (CIM) system, with unit process recipe specifications passed to the AVP host computer for process execution and control. More than 40 AVP systems have been designed and built for applications in TIs advanced silicon integrated circuit and HgCdTe detector technologies. Rapid thermal processes have been developed for all the thermal fabrication steps required in two 0.35 μm CMOS technologies. These processes include thin dielectric growth (dry and wet rapid thermal oxidations), high-pressure field oxidation, high-pressure BPSG reflow, source/drain and gate anneals. CMOS well formation, TiN/TiSi2 react & anneal, forming-gas anneal, and rapid thermal chemical-vapor deposition (RTCVD) processes for amorphous silicon, polysilicon, tungsten, silicon dioxide, and silicon nitride. These RTPs cover a processing temperature range of 450°–1100°C. An integrated sensor system will also be presented for rapid thermal process control. The lamp-heated reactors employ multi-zone axisymmetric illuminators and noinvasive in-situ sensors for real-time process uniformity control and process/equipment diagnostics. Various modes of sensor fusion have been implemented for improved equipment/process control performance. Improved RTP control has been established throughout the integrated CMOS flows using a customized backside seal structure on epitaxial wafers. Complete sub-half-micron CMOS process integration and device manufacturing have been successfully demonstrated with all-RTP thermal processing. Source/drain RTP was shown to decrease the effect of back-end processing on both salicided and unsalicided CMOS 0.25 μm devices.

In-situ monitoring of submicron polysilicon linewidths using diffraction gratings

The measurement of pattern integrity is performed as a part of process control in all wafer manufacturing environments. Typically this measurement is performed off-line on pilot material using a top down scanning electron microscope (SEM). With the advent of sub- micron geometries and small lot wafer fabrication centers, it has become important to monitor the processes on a wafer by wafer basis. An in situ technique using diffraction grating test patterns has been used to monitor the pre-etch and post-etch linewidths on a polysilicon etch chamber. The technique is capable of linewidth measurements to 0.25 microns with pitches as small as 0.7 microns. A comparison of the in situ polysilicon linewidth measurements with off-line SEM measurements shows measurement differences of less than 10% indicating a measurement accuracy on that order. The repeatability of the diffraction technique is shown to be approximately 0.01 micron in comparison to the typical SEM repeatability of 0.025 micron.

Interferometric monitoring and control of silicon incorporation in the diffusion-enhanced silylated resist process

The diffusion enhanced silylated resist or DESIRER process is a well known surface imaging lithographic technique consisting of three steps: exposure, silylation, and dry develop. The success of this method for patterning submicron features depends critically on controlling silicon incorporation in the resist. In this report interferometric data obtained during the resist silylation step and subsequent dry develop etch have been used to correlate silylation parameters and exposure dose with the depth of silicon incorporation. Contrast and linewidth variation as a function of silylation depth have been derived. A kinetics model in conjunction with image intensity simulations has been used to understand the effects of process parameters on pattern quality. The potential of using the interferometric data for process monitoring is also discussed.

Characterization of a high-density plasma source for dry develop

The nature of the dry develop process demands controllable ion energies for good etch selectivity, a large highly directional ion flux for good anisotropy, and a clean etch. As a part of the plasma characterization, the plasma density, the resist etch rate, the ion energy and the ion energy flux have been determined as a function of process conditions, for an inductively coupled plasma (ICP) source. The plasma density and ion flux increase linearly with antenna power. A factor of four variation in ion to neutral flux ratio could be achieved over the rage of flow rates and power levels investigated. Independent control of the etch rate and selectivity is possible with the ICP system. However, eddy current heating of the wafer at high power levels causes loss of anisotropy. Feasibility of using an ICP for the DESIRE process is demonstrated. Good pattern linearity can be achieved for feature sizes ranging from 0.35 - 0.60 micrometers . The process latitude for the exposure time, silylation time, and etch conditions is wide. The etch is clean, exhibits good anisotropy, and no proximity effects. The ICP etch system is an attractive choice for sub half micron patterning using DESIRE.