Pushkar P. Apte

Kinetics and nucleation model of the C49 to C54 phase transformation in TiSi2 thin films on deep‐sub‐micron n+ type polycrystalline silicon lines

A detailed kinetic study of the C49 to C54 phase transformation in TiSi2 thin films was performed, to obtain the full time, temperature, and linewidth dependence of the fraction transformed during rapid thermal annealing on patterned deep‐sub‐micron lines. A Johnson–Mehl–Avrami kinetic analysis showed Avrami exponents of 0.8±0.2 for all submicron lines and 1.9±0.2 for a 40 μm side square structure. The activation energy of 3.9 eV was independent of linewidth. Transformation times increased dramatically as linewidth decreased. A kinetic model based on the density of nucleation sites as a function of linewidth and C49 grain size is proposed and shown to fit the data.

Correlation of trap generation to charge-to-breakdown (Q/sub bd/): a physical-damage model of dielectric breakdown

Ultrathin gate and tunnel oxides in MOS devices are subjected to high-field stress during device operation, which degrades the oxide and eventually causes dielectric breakdown. Oxide reliability, therefore, is a key concern in technology scaling for ultra-large scale integration (ULSI). Here we provide critical new insight into oxide degradation (and consequently, reliability) by a systematic study of five technologically relevant parameters, namely, stress-current density, oxide thickness, stress temperature, charge-injection polarity (gate versus substrate), and nitridation of pure oxide. For all five parameters, a strong correlation has been observed between oxide degradation and the generation of new traps (distinct from the filling of intrinsic traps). Further, we observe that this correlation is independent of the trap polarity (positive versus negative). Based on this correlation, and based on the fundamental link between electronic properties and atomic structure, a physical-damage model of dielectric breakdown has been proposed. The concept of the physical-damage model is that the oxide suffers dielectric breakdown when physical damage due to broken bonds forms a defect-filled filamentary path in the oxide, that conducts excessive current. A good monitor of this physical damage is trap generation, which we believe is caused by physical bond breaking in the oxide and at the interface. The model has been quantified empirically by the correlation between trap generation and Q/sub bd/. >

Use of a TiN cap to attain low sheet resistance for scaled TiSi 2 on sub-half-micrometer polysilicon lines

A new process technology has been demonstrated that successfully addresses an urgent challenge in silicide technology scaling: the formation of low-resistivity TiSi/sub 2/ on sub-half-micrometer polysilicon lines. The key idea is the use of a TiN cap during the silicide process to minimize contaminants and stress in the film. No complex process steps have been added, and the thermal budget actually has been reduced, allowing for easy integration into standard CMOS technology. The new technology enables low sheet resistance values to be attained for scaled-down TiSi/sub 2/ thicknesses on sub-half-micrometer geometries, and thus, is eminently suited for scaling TiSi/sub 2/ technology.

A thickness model for the TiSi2TiN stack in the titanium salicide process module

Abstract A reliable TiSi 2 TiN stack thickness model is an essential component for modeling the titanium salicide process, and such a model is not well-developed in current process simulators and in the literature. To determine this model, a design of experiments was set up to examine five process variables, namely, as-deposited Ti thickness, reaction temperature, reaction time, As + implanted dose, and the reaction ambient pressure. Weight and sheet resistance measurements were used to evaluate the thickness and efficiency of reaction (%Ti converted to suicide). A good first-order linear model was obtained, with a residual standard deviation (variation of model from data) of ~30 A. The model establishes quantitatively, that the TiSi 2 thickness is proportional to the as-deposited Ti thickness and reaction temperature, inversely proportional to the implanted As + dose, and weakly proportional to the reaction time. Since TiN and TiSi 2 are competing reactions, TiN exhibits inverse functional relationships with the variables, as compared with TiSi 2 . The efficiency of the reaction also has been quantified by the model. The ambient pressure has been found to have no impact on either the TiSi 2 TiN stack thickness, or the reaction efficiency. The model has been validated by cross-sectional transmission electron microscopy, which agrees with the model prediction within experimental error.

An integrated approach for accurate simulation and modeling of the silicide-source/drain structure and the silicide-diffusion contact resistance

We present the first integrated simulation and modeling approach for the silicide-source/drain structure, and for the silicide-diffusion contact resistance; thus, providing the critical link between electrical performance and the processing/structural variables forming the silicide source/drain region. We apply this approach to predict the silicide-diffusion contact resistance accurately, and to improve transistor performance significantly.

Process Design & Integration of Salicide and Source/Drain Process Modules for Improved Device Performance

In integrated circuit (IC) fabrication, understanding and optimizing process interactions and variability is critical for swift process integration and performance enhancement, especially at dimensions ≤0.25μm. We present here an approach to address this challenge, and we apply it to improve the process design for two critical modules in a typical CMOS IC process—salicide and source/drain. Together, these modules impact the silicide-to-diffusion contact resistance (R c ), and the gate sheet resistance (R s ); which, in turn, significantly affect transistor series resistance and circuit delays respectively. In our approach, we have investigated a process domain consisting of both silicide and source/drain process variables; and we have developed a quantitative framework for analysis and optimization, along with qualitative insight into underlying the physical mechanisms. We demonstrate that the transistor drive current (I d ) improves by ≈5‥, and circuit performance, as measured by the figure-of-merit (FOM), by ≈4‥. This improvement is significant, and an added benefit is that other transistor characteristics such as effective channel length, off-current, substrate current etc. are affected minimally. Finally, we use this approach to optimize trade-offs such as R c vs R s and performance vs manufacturability; thus enabling manufacturable processes that meet the requirements for high performance.

A model-based approach for process design and its application to the titanium salicide process

Process technology development constitutes a significant cost in manufacturing integrated circuits. In this paper, we present a model-based approach for developing new process technology rapidly and inexpensively, using the salicide process to demonstrate the concepts. This approach is applied to evaluate performance tradeoffs, to develop insight into the underlying process physics, to quantify the impact of the salicide process on the device and circuit performance, and to estimate the process variability. The key idea of this approach is to group a sequence of process steps into a process module, and build simple and accurate process models for the module. The paper also illustrates the use of this model-based approach in synthesizing optimal processes rapidly based on requirements, contributing to the reduction of technology development cost and cycle time.