Akiko Nomachi

Patterning strategy and performance of 1.3NA tool for 32nm node lithography

We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects.

Immersion resist process for 32-nm node logic devices

Key issues of resist process design for 32nm node logic device were discussed in this paper. One of them is reflectivity control in higher 1.3NA regime. The spec for the reflectivity control is more and more severe as technology node advances. The target of reflectivity control over existent substrate thickness variation is 0.4%, which was estimated from our dose budget analysis. Then, single BARC process or stacked mask process (SMAP) was selected to each of the critical layers according to the substrate transparency. Another key issue in terms of material process was described in this paper, that is spin-on-carbon (SOC) pattern deformation during substrate etch process. New SOC material without any deformation during etch process was successfully developed for 32nm node stacked mask process (SMAP). 1.3NA immersion lithography and pattern transfer performance using single BARC

Patterning performance of hyper NA immersion lithography for 32nm node logic process

We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.

Feasibility of Ultra-Low k1 Lithography for 28nm CMOS Node

We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the 28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask topography effect and the oblique-incidence. Using the rigorous lithography simulation considering the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum pitch required in 28nm node. The optimum mask plate and illumination conditions have been decided by simulation. The experimental results for 28nm node show that the minimum pitch patterns and minimum SRAM cell are clearly resolved by single exposure.