Katsura Miyashita

Patterning strategy and performance of 1.3NA tool for 32nm node lithography

We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects.

Improved Ti Self-Aligned Silicide Technology Using High Dose Ge Pre-Amorphization for 0.10 µm CMOS and Beyond

Improved Ti self-aligned silicide (SALICIDE) technology for 0.1 µm complimentary metal-oxide-semiconductor (CMOS) using high dose pre-amorphization implantation (PAI) is developed. High dose PAI with As and Ge promotes the growth rate of silicidation on polycrystalline silicon gate even when its length is reduced to 0.1 µm. Thus it achieves low sheet resistivity at narrow lines. In addition, the advantage of Ge over As as PAI species is confirmed. Ge PAI does not affect the parasitic resistance increase of p channel metal-oxide-semiconductor field effect transistor (pMOSFET) or junction leakage characteristics because of its electrical neutrality and high solubility in silicon.

Patterning performance of hyper NA immersion lithography for 32nm node logic process

We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.

Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond

Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond J.-P. Han, T. Shimizu, L.-H. Pan, M. Voelker, C. Bernicot, F. Arnaud, A. C. Mocuta, K. Stahrenberg, A. Azuma, G. Yang, M. Eller, D. Jaeger, H. Zhuang, K. Miyashita, K. Stein, D. Nair, J.-H. Park, M. Hamaguchi, S. Kohler, D. Chanemougame, W. Li, K Kim, N. Kim, C. Wiedholz, S. Miyake, G. Tsutsui, H. van Meer, J. Liang, M. Ostermayr, J. Lian, M. Celik, R. Donaton, K. Barla, M.H. Na, Y. Goto, M. Sherony, F. Johnson, R. Wachnik, J. Sudijono,E. Kaste, R. Sampson, J.-H. Ku, A. Steegen, W. Neumueller Infineon Technologies, Renesas, IBM Microelectronics, STMicroelectronics, Toshiba America, GLOBALFOUNDRIES, Samsung Electronics, alliances at IBM SRDC, 2070 Rt 52, Hopewell Junction, NY12533; jh262@ieee.org,

Feasibility of Ultra-Low k1 Lithography for 28nm CMOS Node

We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the 28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask topography effect and the oblique-incidence. Using the rigorous lithography simulation considering the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum pitch required in 28nm node. The optimum mask plate and illumination conditions have been decided by simulation. The experimental results for 28nm node show that the minimum pitch patterns and minimum SRAM cell are clearly resolved by single exposure.