Akiyoshi Hatada

Physical and electrical analysis of the stress memorization technique (SMT) using poly-gates and its optimization for beyond 45-nm high-performance applications

We have investigated the stress memorization technique (SMT) using poly-gates through both physical analysis and electrical characterization. It has been clarified that channel compressive strain in the vertical direction originates from poly-gate volume expansion, which is associated with both grain growth and highly concentrated impurities implanted into gates. By optimizing key factors in the SMT process with arsenic (As) source/drain (SD), we have achieved competitive NFET drive current compared to that with phosphorus (P) SD with lower parasitic resistance which requires extra offset spacers for SD implantation. For further scaling of gate pitches beyond 45-nm node and enhancing NFET performance, well-optimized SMT with As-NSD is indispensable technology for both poly and metal gates.

Tungsten Film Chemical Mechanical Polishing Using MnO2 Slurry

It has been demonstrated that MnO2 abrasive can polish tungsten films without using an oxidizer solution. The polishing rate of MnO2 slurry is 1.5 times higher than that of commercially available Al2O3 slurry. A W plug is formed without etching holes (keyholes) during chemical mechanical polishing with MnO2 abrasive slurry. With MnO2 slurry, no key holes were formed even after overpolishing by an additional 0.6 µm. On the other hand, with conventional Al2O3 slurry, keyholes were formed after overlpolishing by an additional 0.4 µm. The residual MnO2 abrasive on the surface after chemical mechanical polishing was completely removed by the cleaning process because MnO2 abrasive easily dissolves in a cleaning solution of HCl, H2O2, and H2O. These results indicate that, since MnO2 is in itself a solid oxidizer, MnO2 abrasive can polish W films without using an oxidizer solution and does not etch the seam.

Advanced junction profile design scheme by low-temperature millisecond annealing and co-implant for high performance CMOS

We found that the relatively low temperature millisecond annealing at S/D activation for nFET is enhanced the co-implanted halo activation regardless of sequence of MSA and spike-RTA. Tilt-and-twist extension implantation technique with millisecond extension annealing for pFET was also performed to reduce the parasitic resistance. By combining these technique, an aggressively scaled high-performance bulk CMOS transistors with world competitive nFET and pFET drive currents of 1282/835 muA/mum at 100 nA/mum off-current at Vd = 1 V and Lg = 34 nm respectively, were developed with a conventional poly/SiON gate stack. The developed CMOS transistors not only have high-performance but also manufacturing friendly and cost effective compared with metal/high-k stack devices.

Potential of and issues with multiple-stressor technology in high-performance 45 nm generation devices

In this paper, we describe multiple-stressor technology (MST) for high-performance 45-nm-node devices. The combination of two or more stressors, namely, polygate stressor (PGS)/tensile stress liner (SL) for n-channel field-effect transistor (NFET), and embedded SiGe/compressive SL for p-channel field-effect transistor (PFET), is integrated into complementary metal–oxide–semiconductor (CMOS) process and its potential for device performance enhancement is investigated. Moreover, the issues of MST are also discussed from the viewpoint of variations in device characteristics under an extremely high channel strain, which are not pronounced in the previous technology with its relatively low strains.

Design and Optimization of Gate Sidewall Spacers to Achieve 45 nm Ground Rule for High-Performance Applications

In this paper, we describe our triple sidewall spacer scheme to achieve 45 nm ground rule for high-performance applications. This triple sidewall spacer scheme uses three kinds of sidewall spacers, in which the first sidewall is used for the source/drain extension implantation offset (SW1), the second is for the p-channel field effect transistor (PFET) embedded silicon germanium offset (SW2), and the third spacer is for the deep source/drain implantation offset (SW3). We also evaluated the impact of sidewall spacer materials and structures on device characteristics. After optimizing each sidewall spacer material and structure including offset width, we successfully demonstrated identical device characteristics with the minimum poly-pitch layout while minimizing layout dependence. This sidewall spacer scheme has the capability to achieve the 45 nm ground rule, and our sidewall spacer design is mature and suitable for 45-nm-node high-performance applications.