Yosuke Shimamune

Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the Ion of 33-nm CMOS devices (8.2% / 12.8% with an Ioff = 9 [nA/mum] for PMOS / NMOS). We also demonstrate that the fluorine co-implant plays a large role in reducing the PMOS source-drain extension (SDE) resistance.

Embedded silicon germanium (eSiGe) technologies for 45nm nodes and beyond

This paper reviews main technologies of embedded silicon germanium (eSiGe) for 45 nm node and beyond .There are three key techniques and an item to be considered carefully as follows. The first technique is a low temperature of epitaxial growth at 550degC to suppress stacking faults in eSiGe layer. The second one is a controlling of recess shape for eSiGe. Sigma(Sigma)-shaped recess is applied, because the strain force on the channel of MOSFET is increased effectively by narrowing spacing between source and drain. The third one is to apply particular surface pre-cleaning treatment before the epitaxial growth, to get the excellent SiGe crystallinity. The final item to be considered carefully is boron concentration in eSiGe, because excessive boron compensates the strain in eSiGe as well as carbon. Finally We demonstrated the Ion = 0.795 mA/mum@Ioff = 100 nA/mum using above key techniques and an item.

Advantages of a New Scheme of Junction Profile Engineering with Laser Spike Annealing and Its Integration into a 45-nm Node High Performance CMOS Technology

We developed a novel junction profile engineering technique that uses laser spike annealing (LSA): LSA is implemented prior to spike-RTA to modulate the junction profile. With this technique, we can improve the performance of MOSFETs more effectively than conventional techniques. In addition, it enables us to use lower LSA temperatures with wide process window (at least 60degC) because of its low sensitivity to LSA temperatures within a certain range, while the conventional ways require ultra high temperatures to improve the device performance. We applied this technique to 45-nm node high performance (HP) CMOS devices with a gate length of 32-nm. A reduction in the source-drain parasitic resistance achieves 8.8% / 5% of improvements in the saturation on-current (Ion) for PMOS / NMOS, and Ion = 750(P) / 1030(N) [muA/mum] for Ioff = 100 [nA/mum] at Vdd= 1.0V. We also demonstrated the advantages of this technique by evaluating the performance of ring oscillators, SRAM yields and accuracy of precision poly resistors from the LSI manufacturing point of view.

Novel Stack-SIN Gate Dielectrics for High Performance 30 nm CMOS for 45 nm Node with Uniaxial Strained Silicon

Aggressively scaled 30nm gate CMOSFETs for 45nm node is reported. We successfully improved a higher drive current with keeping the short channel effect by Sigma shaped SiGe-source/drain (Sigma SiGe) structure using compressive-stressed liner. In addition, we developed novel stack-SIN gate dielectrics by using bis-tertiarybutylamino-silane (BTBAS)/NH3. Novel stack-SIN gate dielectrics show higher immunity to negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) lifetime compared with conventional plasma nitrided silicon dioxide. These characteristic are originated from its unique nitrogen profile. The nitrogen concentration is over 22% at the surface of the dielectric and it rapidly decreases to 1% at the interface with a substrate. A high performance 30 nm gate nMOSFET and pMOSFET were demonstrated with a drive currents of 1042 muA/mum and 602 muA/mum at Vd = 1 V / Ioff=100 nA/mum, respectively

Advanced junction profile design scheme by low-temperature millisecond annealing and co-implant for high performance CMOS

We found that the relatively low temperature millisecond annealing at S/D activation for nFET is enhanced the co-implanted halo activation regardless of sequence of MSA and spike-RTA. Tilt-and-twist extension implantation technique with millisecond extension annealing for pFET was also performed to reduce the parasitic resistance. By combining these technique, an aggressively scaled high-performance bulk CMOS transistors with world competitive nFET and pFET drive currents of 1282/835 muA/mum at 100 nA/mum off-current at Vd = 1 V and Lg = 34 nm respectively, were developed with a conventional poly/SiON gate stack. The developed CMOS transistors not only have high-performance but also manufacturing friendly and cost effective compared with metal/high-k stack devices.

Integration Strategy of Embedded SiGe S/D CMOS from Viewpoint of Performance and Cost for 45nm-Node and Beyond

Direct comparison between competitive process flows showed that the eSiGe-S/D-last flow is the most promising CMOS integration process for manufacturing 45-nm technology node and beyond because it has good extensibility with various performance boosters, has fewer process steps and suppresses electrical fluctuations. The eSiGe-S/D-last (after offset spacer + I.I.) flow creates a sufficient process window that comprehensively optimizes both channel strain, induced by eSiGe-S/D (proximity, elevated height, and uniformity), and carrier profiles (offset spacer and thermal budget including millisecond annealing). An optimized eSiGe-S/D with a low thermal budget and amorphous Si gate decreases electrical fluctuations resulting in continuous scaling and a lower manufacturing cost.

Technology Breakthrough of Low Temperature, Low Defect, and Low Cost SiGe Selective Epitaxial Growth (L 3 SiGe SEG) Process for 45nm Node and Beyond

We have developed low temperature, low defect and low cost SiGe selective epitaxial growth (L3 SiGe SEG) process using a high throughput batch type CVD process at first time. Defect is eliminated by low temperature pre-cleaning and recess shape control. As a result, we have achieved the high quality SiGe SEG, improving the compressive channel stress and reducing the junction leakage. We also improved the NMOS short channel effects by low temperature SiGe SEG. Finally, in combination of low temperature SiGe SEG, dual stress SiN liner, and low thermal budget metallization, drive current of 725 muA/mum in PMOS and 940 muA/mum in NMOS were achieved at off current (Ioff) =100 nA/mum at drain bias (VDD) = 1.0 V.

Stress variability control by defects suppression of SiGe Source/Drain using novel SiGe epitaxial growth technique

Abstract We found that pits near the recessed Si side wall of pMOSFET with eSiGe degrade the device variability due to local tensile strain induced in the channel region. This was improved by newly developed SiGe epitaxial growth technique that includes two-step sequences with different amount of additional HCl in SiH4-GeH4-B2H6-HCl-H2 gas mixtures. By using this technique, we achieved saturation drain current (Ion) increase (4%) and improvement both in Ion and threshold voltage variability.

Principal Guideline of Stress Design Engineering for Drivability Enhancement and Suppression of Variability in PMOSFET with SiGe S/D

We have developed the guideline for stress design engineering with embedded Silicon Germanium (eSiGe) source drain (S/D) technology. It enables us to improve drivability and to suppress the variety in Vth. Based on this guideline, the minimization of Si loss above extension region is performed not only to improve drivability enhancement but also to suppress variation in Vth in PMOSFET due to suppression of dislocations which are generated at channel edges. This technique controls stress discontinuity at channel edge, hence enables us to use our new high Ge-mole-fraction profile to enhance the mobility. Furthermore, by optimization of MSA temperature, we successfully avoided stress relaxation of eSiGe even in high Ge-mole-fraction condition. Consequently, this stress technique realized a 19.2 % improvement in Ion for Ioff = 100 [nA/ m] at Vd = 1.0 [V], and Ion = 809 [ A/ m] was successfully achieved, while variety in Vth was kept as low as reference with box Ge profile. We also demonstrate that this scheme was compatible with NMOSFETs.