Masashi Shima

channel strained-SiGe p-MOSFET with enhanced hole mobility and lower parasitic resistance

Employment of <100> channel direction in a strained-Si/sub 0.8/Ge/sub 0.2/ p-MOSFET has demonstrated the substantial amount of hole mobility enhancement as large as 25% and parasitic resistance reduction of 20% compared to a <110> strained-Si/sub 0.8/Ge/sub 0.2/ Channel p-MOSFET, which already has an advantage in mobility and the threshold voltage roll-off characteristic over the Si p-MOSFET. This result indicates that the <100> strained SiGe channel p-MOSFET is a promising and practical candidate for realizing high-speed CMOS devices under low-voltage operation.

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets

The recent rapid spread of smart-phone use has resulted in a strong demand for a multi-band RF part with reduced size and power consumption. In the creation of an ideal RF system-on-a-chip, the biggest challenge is to realize a fully integrated PA in CMOS. In conventional PAs in compound semiconductor technologies, face-up wire-bond assembly with off-chip matching components is typically used, but flip-chip packaging is more suitable for slim mobile phones in which low-profile components are desired as well as for future integration with an RF transceiver in which the same packaging scheme is widely used. The PA for GSM [1] was insufficient for our target, so we needed to greatly improve the linearity in order to comply with the W-CDMA standard, which has better frequency-usage efficiency. Conventional CMOS PAs only support a single band [2,3] or are for WLAN [4] where the output power level is low (typically about 20dBm). In this paper, we present a fully-integrated triple-band linear CMOS PA for W-CDMA. Its flip-chip package is just 3.5×4×0.7mm3, and the average current consumption is less than 20mA.

High RF power transistor with laterally modulation-doped channel and self-aligned silicide in 45nm node CMOS technology

A novel high RF power MOSFET was developed to integrate a high-power amplifier into 45 nm node CMOS technology. A self-aligned silicide and laterally modulation-doped channel attained the lowest on-resistance of 1.7 Omega-mm with a high breakdown voltage of more than 10 V and successfully achieved the highest output power density of 0.6 W/mm at the maximum power-added efficiency ever reported among CMOS high breakdown voltage transistors. The reduced gate resistance led to a high frequency characteristic of 43 GHz fmax. We also confirmed that the optimized profile of a gate-overlapped lightly doped drain provides sufficient HC and TDDB reliabilities with a gate oxide as thin as a 3.3 V I/O transistor. These results indicate that a single-chip CMOS transceiver with a high-power amplifier can be produced in advanced CMOS fabs.

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Youngs modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was also carefully optimized for low leakage current. As a result of a 12% mobility improvement and a 30% Rsd reduction, enhancements of 19 and 14% and Ion(@Ioff= 5 nA/mum) of 620 and 830 muA/mum were achieved for NMOS at 0.85 and 1.0V, respectively. As a result of a 45% mobility improvement and a 25% Rsd reduction, the enhancements of 32 and 22% and Ion of 330 and 440 muA/mum were achieved for PMOS at 0.85 and 1.0V, respectively. These results are the best Ion-Ioff tradeoff characteristics among the recent LOP transistors

0.3-μm gate length p-channel AlGaAs/InGaAs heterostructure field effect transistors with high cut-off frequency

P-channel Heterostructure Field Effect Transistors (HFETs) with a 0.3-/spl mu/m gate were fabricated by Mg ion implantation. The maximum transconductance was 68 mS/mm and there was no serious drain or gate leakage current, regardless of this short gate length. The gate turn on voltage (@I/sub gs/=-1 /spl mu/A//spl mu/m) was -2.1 V and its absolute value was large enough for use in complementary HFETs. S-parameters measurements showed a very high cut-off frequency of over 10 GHz. Results indicated the superiority of less-diffusive Mg ion implantation for forming p/sup +/-layer in p-channel HFETs.

Random telegraph signals of tetrahedral-shaped recess field-effect transistor memory cell with a hole-trapping floating quantum dot gate

An AlGaAs/InGaAs heterojunction field-effect transistor (FET) memory cell in a tetrahedral-shaped recess (TSR) on the (111)B GaAs substrate was fabricated and investigated. The TSR–FET memory cell has a channel on the (111)A facet surfaces of the recess and a hole-trapping quantum dot (QD) as a floating gate at the bottom. Memory operations were achieved at temperatures up to 130 K, and random telegraph signals (RTSs) with a temperature dependence were observed in the retention characteristics. After our analysis of RTSs, the activation energy of hole capture and emission processes in the TSR QD were estimated to be 260 and 190 meV, respectively.

Novel Stack-SIN Gate Dielectrics for High Performance 30 nm CMOS for 45 nm Node with Uniaxial Strained Silicon

Aggressively scaled 30nm gate CMOSFETs for 45nm node is reported. We successfully improved a higher drive current with keeping the short channel effect by Sigma shaped SiGe-source/drain (Sigma SiGe) structure using compressive-stressed liner. In addition, we developed novel stack-SIN gate dielectrics by using bis-tertiarybutylamino-silane (BTBAS)/NH3. Novel stack-SIN gate dielectrics show higher immunity to negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) lifetime compared with conventional plasma nitrided silicon dioxide. These characteristic are originated from its unique nitrogen profile. The nitrogen concentration is over 22% at the surface of the dielectric and it rapidly decreases to 1% at the interface with a substrate. A high performance 30 nm gate nMOSFET and pMOSFET were demonstrated with a drive currents of 1042 muA/mum and 602 muA/mum at Vd = 1 V / Ioff=100 nA/mum, respectively

Tetrahedral-shaped recess [111]A facet channel AlGaAs/InGaAs heterojunction field-effect transistor with an InGaAs floating quantum dot gate

A transistor and memory operation of a new AlGaAs/InGaAs heterojunction field-effect transistor (HFET) in a tetrahedral-shaped recess (TSR) on the [111]B GaAs substrate was investigated at a temperature up to 120 K. The TSR-FET memory has a channel on the [111]A side surfaces of the recess and a single floating quantum dot (QD) gate at the bottom. Owing to the particular shape of the TSR structure, the charge in the floating QD gate can effectively modulate the channel current. We found a clear hysteresis in the current-voltage (I-V) characteristics with an abrupt increase and decrease in the current at the subthreshold gate bias region. Random telegraph signals with a constant amplitude of about 70 nA were also observed in the memory retention characteristics. These phenomena were considered to be attributed to the current modulation by hole charging/discharging in the QD.

High drive current NMOS with Si-SiGe heterostructure low electric field channel

A drive-current enhancement in NMOS with a compressively strained SiGe structure, which had been a difficult challenge for CMOS integration with strained SiGe high-hole-mobility PMOS, was successfully achieved using a Si-SiGe heterostructure low electric field channel of optimum thickness. A 4-nm-thick Si low-field-channel NMOS with a 4-nm-thick Si/sub 0.8/Ge/sub 0.2/ layer improved drive current by 10% with a 20% reduction in gate leakage current compared with Si-control, while suppressing threshold-voltage rolloff characteristic degradation, and demonstrated excellent I/sub on/--I/sub off/ characteristics of I/sub on/ = 1 mA//spl mu/m for I/sub off/ = 100 nA//spl mu/m. These results are the best in ever reported NMOS with a compressively strained SiGe structure and indicate that a Si-SiGe heterostructure low-field-channel NMOS integrated with a compressively strained SiGe channel PMOS is a promising candidate for high-speed CMOS in 65-nm node logic technology.

Electron transport through tetrahedral-shaped recess (TSR) stacked double quantum dot structures

We formed a stacked double TSR quantum dot structure and measured its I-V characteristics. The fine structure related to TSR quantum dots was observed in the low bias region, while negative differential resistances on the order of /spl mu/A were observed in the higher bias region. The fine structure is well explained by the resonant tunneling through individual TSR quantum dot states.