Alan Cuthbertson

Investigations on the impacts of misalignment in the integration of 0.18-μ multilevel interconnect

As technology continues to shrink with tighter design rules, it becomes inevitable for the integrated process to demand a more stringent control over the in-line parameters. For multilevel interconnect, each processing step in the formation of every layer of via plug and metal interconnect impacts the overall performance and yield of the silicon wafer. The control of the process thus becomes even more challenging as more layers of interconnect are required to meet the speed performance and density requirements. The success of the integration of the multilevel interconnect is governed by the performance of every unit module which contributes to the build-up of the interconnect. This is especially true for the masking or lithography module that is well known to be the forefront driver in the make-up of a new Integrated Circuit generation. Related lithography parameters that are generally used to investigate the process performance include control of critical dimensions (CD) of via and metal line, metal island as passing metal pad and overlay or misalignment. In this paper, we have chosen to investigate the impacts of misalignment on the interconnect. In addition, we also contrast and discuss the effects of exposed via plug due to CD variations, misalignment and metal EOL shortening. For these, we design an experiment that takes into account the top and bottom metal CD, via CD and misalignment. The response in the parametric via resistance is elaborated in detail to show the robustness of the interconnect, taking into account the worst case that can possibly be encountered in mass production. Whilst misalignment of via plug and metal lines tend to increase the via resistance, we demonstrate that the impact on the interconnect may be different for different density of via test structure. We also discuss a critical mode of failure despite having shown its robustness in the earlier section of this paper. We disclose the root cause and explain the mechanism of failure.