Wuping Liu

Challenges of Ultra low-k integration in BEOL interconnect for 45nm and beyond

This paper presents some major integration challenges in Ultra low-k (ULK) Back-End-Of-Line (BEOL) interconnects for 45nm and beyond. The discussions mainly address the challenges that arise from ultra violet (UV) curing that cause changes in the composition of Nitrogen doped Silicon Carbide (SiCN), poor mechanical strength of ULK, Reactive Ion Etching (RIE) and barrier deposition plasma induced damage at the sidewall and the bottom of the trench, and gap-fill limitation of the copper (Cu) process. The physical characterization and Resistance-Capacitance (RC) results of the ULK integration are also presented.

Effect of chemical mechanical polishing scratch on TDDB reliability and its reduction in 45nm BEOL process

The correlation of time-dependent dielectric breakdown (TDDB) reliability failure with scratches generated from chemical mechanical polishing (CMP) in 45nm backend-ofline (BEOL) process is investigated and established. The wafer map of early TDDB failure samples matches well with the defect wafer map from bright field scans. Electrical fault isolation using thermally induced voltage alteration (TIVA) analysis is employed to locate the hot spot where TDDB leakage occurs. Polish scratchinduced metal damage at the hot spot is further analyzed by topdown scanning electron microscopy (SEM) after de-processing. Also, the depth of the polish scratch is confirmed by using transmission electron microscopy (TEM) analysis. It clearly shows that the embedded particle on copper (Cu) surface and the liner damage resulted from polish scratch severely affect the TDDB reliability. In-situ CMP platen3 (P3) pad chemical preclean is found to reduce the polish scratch density effectively and significantly improve the V-ramp/TDDB reliability performance. However, inappropriate usage of chemical pre-clean would cause Cu corrosion and lead to EM degradation. Hence, a balance between polish scratch reduction and Cu corrosion associated with P3 pad pre-clean needs to be achieved.

The effects of dielectric slots on Copper/Low-k interconnects reliability

The effects of dielectric slots on Cu/Low-k interconnects reliability were studied. Dielectric slots were proven to be effective in suppressing stress-induced void failure but their impact on EM reliability was found to be minimal. Physical failure analysis and finite element simulations were used to explain the possible mechanisms associated to the different effects of dielectric slots on Cu/low-k reliability.