Aleksandra Drozd

Measurements of Matching and Noise Performance of a Prototype Readout Chip in 40 nm CMOS Process for Hybrid Pixel Detectors

The paper presents a prototype integrated circuit built in a 40 nm CMOS process for readout of a hybrid pixel detector. The core of the IC constitutes a matrix of 18 ×24 pixels with the pixel size of 100 μm ×100 μm. The paper explains the functionality and the architecture of the IC, which is designed to operate in both the standard single photon counting mode and the single photon counting mode with interpixel communication to mitigate negative effects of charge sharing. This article focuses on the measurement results of the IC operating in the standard single photon counting mode. The measured ENC is 84e- rms (for the peaking time of 48 ns), the gain is 79.7 μV/e-, while the effective threshold dispersion is 21e- rms.

FPGA Simulations of Charge Sharing Effect Compensation Algorithms for Implementation in Deep Sub-Micron Technologies

This article describes the advantages of using the Field Programmable Gate Arrays (FPGA) for significant acceleration of Monte Carlo simulations leading to the fast verification of new ideas. An example of a real and challenging problem in the design of application specific integrated circuits (ASIC) for 2D X-ray imaging applications, namely the charge sharing effect in a highly segmented position sensor, is presented together with a detailed description of its software and hardware simulations. The implementation of the C8P1 algorithm is described at the hardware simulation level, including mathematical modeling parameters and tools used. As a result of the presented approach, simulations over 1000 times faster (compared to standard processor driven) are possible, reducing multi-dimensional simulation duration from days to minutes. The presented solution has helped identify and improve weak points in numerous versions of the C8P1 algorithm to mitigate the charge sharing effect and to implement an ASIC in ultra-deep sub-micron solution technology, which aims to improve medical, scientific and industrial X-ray imaging in terms of spectral and position sensitive measurements.

A pixel readout chip in 40 nm CMOS process for high count rate imaging systems with minimization of charge sharing effects

We present a prototype chip built in a 40 nm CMOS process for readout of a pixel detector. The prototype chip has a matrix of 18×24 pixels with a pixel pitch of 100 μm. It can operate in both: the single photon counting (SPC) mode and the C8P1 mode. In the SPC mode using the high gain setting the measured ENC is 84 e- rms (for the peaking time of 48 ns), the gain is 79.7 μV/e-, while the effective offset spread is 24 e- rms. In the C8P1 mode, the chip reconstructs full charge deposited in the detector, despite the charge sharing, and it points to a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.

A new approach for a cameras backend design for the 75 µm pitch hybrid pixel detector

We report on the design of a portable X-Ray camera working in single photon counting mode and a very high frame rate exceeding 20000 fps. The camera consists of hybrid pixel detector, where a two readout ASICs consisting of 23552 pixels of 75um pitch are used. A new approach is used for designing the camera using the commercially available controller board supplied with Zynq FPGA, ARM controller and custom PCB integrating readout chips bump-bodnded to the silicon sensor, power supply, variety of communication ports including USB, Ethernet and Camera Link. All levels of the system (FPGA, microcontroller and Windows Application) are programmed with National Instruments LabVIEW allowing extreme acceleration of developing process due to single software platform.

Design of the ultrafast LVDS I/O interface in 40 nm CMOS process

This paper presents the design and simulation results of the ultrafast LVDS I/O interface designed in 40 nm CMOS process. The LVDS transmitters and receivers were designed to support a data transfer of a multichannel Integrated Circuit dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The transmitter is based on the current switching bridge architecture while the receiver is built of the inverting comparator with hysteresis. The LVDS I/O interface is supplied from 2.5 V and 0.9 V supply voltage. The transmitter and receiver occupy respectively 0.1 mm2 and 0.009 mm2 of chip area. The static/dynamic power consumption of the transmitter and receiver are respectively equal to 17.9/26.4 mW and 7.1/12.1 mW.

Ultra fast X-ray detection systems in nanometer and 3D technologies

For many years hybrid pixel detectors working in the single photon counting mode have been used not only in high energy physics experiments but also for X-ray imaging applications. In these detectors each pixel has its independent electronic readout channel for photon by photon signal processing, what provides better image quality and possibility of counting photons only within a given energy window. There are different trends in development of hybrid pixel detectors. One is to use nanometer or 3D technologies to include more complex functionality in single pixel cell together with good parameters of analog front-end electronics and high maximum pulse throughput per single channel. Another trend is targeted at building large area X-ray cameras which can be used by industry or novel scientific experiments mainly in material science, physics and biology. In both trends the problems to be solved are similar, however the priorities are a little bit different. This paper presents the main issues related to the development of semiconductor pixel detector systems on the examples of produced integrated circuits.