Rafal Kleczek

Measurements of Matching and Noise Performance of a Prototype Readout Chip in 40 nm CMOS Process for Hybrid Pixel Detectors

The paper presents a prototype integrated circuit built in a 40 nm CMOS process for readout of a hybrid pixel detector. The core of the IC constitutes a matrix of 18 ×24 pixels with the pixel size of 100 μm ×100 μm. The paper explains the functionality and the architecture of the IC, which is designed to operate in both the standard single photon counting mode and the single photon counting mode with interpixel communication to mitigate negative effects of charge sharing. This article focuses on the measurement results of the IC operating in the standard single photon counting mode. The measured ENC is 84e- rms (for the peaking time of 48 ns), the gain is 79.7 μV/e-, while the effective threshold dispersion is 21e- rms.

A bidirectional 64-channel neurochip for recording and stimulation neural network activity

We present the design and measurements of a novel 64 channel ASIC dedicated for recording and stimulation of neural network activity. Chip is designed in submicron CMOS 180nm technology, occupies 5×5 mm2 of silicon area, and consumes only 25 μW/channel. The low cut-off frequency can be tuned in the range 60 mHz-100 Hz while the mean high cut-off frequency is 4.7 kHz or 12 kHz. The recording channel voltage gain may be also changed. Mean measurement values show it may be either 139 V/V or 1100 V/V. The measured input referenced noise is 3.7 μV rms in band 100 Hz-12 kHz and 7.6 μV rms in band 3 Hz-12 kHz. For the input signals amplitude 1.5 mV, the THD is 1%. In order to satisfy requirements concerning spread of the main parameters of the multichannel system, each channel is equipped with the two corrections DACs. These allow to obtain voltage gain equal to 139 V/V with the standard deviation std = 0.67 V/V, and low cut-off frequency equal to 60 mHz with the std = 30 mHz only. Each channel is equipped additionally with a stimulation circuits allowing to generate stimulation pulses in the 125 nA-512 μA current range with 8-bit resolution. All ASIC configurations are set thanks to on-chip digital register controlled by the on-chip LVDS receivers.

Time and energy measuring front-end electronics for long silicon strip detectors readout

We report on the design of a self-triggered analog front-end readout electronics dedicated for signal detection from double-sided silicon microstrip sensors with capacitance at the order of tens pF (CDET ≈ 30 pF). The main requirements are: processing input pulses with the average rate of 150 kHz/channel, low power consumption and low noise at the same time. The single channel is built of two different parallel processing chains: the fast and slow. The fast path includes: a fast CR-RC shaper with the peaking time tp = 40 ns, a discriminator, a pulse stretcher and a time stamp latch. It is optimized to determine an input charge arrival time with resolution at the order of few ns. The slow path consists of: a slow shaper with the peaking time tp = 80 ns, a 5-bit flash ADC and a digital peak detector. This chain is dedicated for accurate energy measurement and it is optimized for low noise level. To protect against false noise-related hits coming from noisy fast processing path when the discrimination threshold is set low, the time-stamp validation circuit is used. Two prototype ASICs were implemented in UMC 180 nm CMOS technology: 8-channel AFE-XYTER and 128-channel STS-XYTER.

STS-XYTER, a high count-rate self-triggering silicon strip detector readout IC for high resolution time and energy measurements

We report on the design of a 128-channel ASIC named STS-XYTER (Silicon Tracking System - X - Y - Time -Energy Read-out) dedicated for signal detection from doublesided silicon microstrip sensors with high capacitance (CDET ≈ 30 pF). The STS-XYTER contains: 128 charge processing channels, a calibration unit, a biasing circuitry based on built-in band-gap reference source and a full digital back-end, which provides synchronization, control and sparsified fast data readout through four, 250 MHz DDR LVDS links based on the CBMnet protocol. The single readout channel uses two parallel signal processing paths (fast and slow) to handle an average rate of input pulses equals 150 kHz and provide an information about both interaction time and deposited charge with good noise performance and low power consumption (6.2 mW/channel) at the same time. The fast path, which is dedicated for determining the input charge arrival time, is built of: a fast shaper, a discriminator, a pulse stretcher and a time stamp latch. The slow path, which is optimized for a particle energy measurement, consists of a slow shaper, a 5-bit flash ADC and a digital peak detector.

FSDR16—Fast and Low Noise Multichannel ASIC With 5th Order Complex Shaping Amplifier

We report on the design and measurements of a multichannel ASIC FSDR16 prototype implemented in UMC 180 nm CMOS technology and dedicated for the readout of silicon strip detectors. The FSDR16 chip contains 16 channels with the size of 60 μm × 880 μm each, which are built with: charge sensitive amplifier, pole-zero cancellation circuit, 5th order complex shaper based on the follow-the-leader architecture and 7-bit trim DAC. To achieve low noise performance and high speed analog signal processing, the proper signal shaping has to be involved in order to obtain voltage pulse which is as symmetrical and short as possible at the shaper output. The functionality of the chip allows to make a comparison between a typical CR-(RC)5 shaper based on real poles and a complex semi-Gaussian shaper based on complex poles. We present both, the design procedure of such filters and the measurements results with the emphasis on the spread of analog front-end parameters of these architectures in the multichannel system. The FSDR16 chip characterizes low power dissipation Pdiss = 3.5 mW per single channel. The peaking time tp measured from 1% to the peak of complex semi-Gaussian shaper is set to 75 ns (fast mode) or 180 ns (slow mode). Its architecture allows to obtain a shorter pulse width tw (t w/tp = 2.85) measured form 1% to 1% of the curve than in case of a typical CR-(RC) 5 shaper (tw/t p = 3.54). The front-end electronics has been optimized for detector capacitance of CDET = 30 pF and for fast mode of complex semi-Gaussian shaper an equivalent noise charge ENC = 172 e- +26.2 e- /pF, while for slow mode ENC = 139 e-+18.9 e-/pF.

Design and measurements of low power multichannel chip for recording and stimulation of neural activity

A 64-channel Neuro-Stimulation-Recording chip named NRS64 for neural activity measurements has been designed and tested. The NRS64 occupies 5×5 mm2 of silicon area and consumes only 25 μW/channel. A low cut-off frequency can be tuned in the 60 mHz - 100 Hz range while a high cut-off frequency can be set to 4.7 kHz or 12 kHz. A voltage gain can be set to 139 V/V or 1100 V/V. A measured input referenced noise is 3.7 μV rms in 100 Hz - 12 kHz band and 7.6 μV rms in 3 Hz - 12 kHz band. A digital correction is used in each channel to tune the low cut-off frequency and offset voltage. Each channel is equipped additionally with a stimulation circuit with an artifact cancellation circuit. The stimulation circuit can be set with 8-bit resolution in six different ranges from 500 nA - 512 μA range.

A flexible, low-noise charge-sensitive amplifier for particle tracking application

This paper presents characteristics and layout of an integrated charge-sensitive amplifier for the multichannel front-end electronics. The design constraints and requirements are based on the Compressed Baryonic Matter experiment two detector layers: Silicon Tracing System working with silicon strip detectors and the Muon Chamber working with gas detectors. The amplifier is designed for low-power (<;10 mW/channel) and low-noise operation within the operating conditions of two different detectors. The circuit also implements solutions for handling mismatch, detector failure, and corner conditions. The emphasis is also put on the power rail design and analysis of leakage current impact on noise.

Noise optimization of the time and energy measuring ASIC for silicon tracking system

This paper presents multi-objective optimization of a front-end electronics implemented in multichannel integrated circuit for silicon sensors readout in the Silicon Tracking System in the CBM experiment at the FAIR center. We present the optimization towards low-power (<; 8 mW/channel) and low-noise while keeping the channel pitch of 58 μm and minimum number of external components required for the circuits operation. Detailed study of the system noise (equivalent noise charge) with respect to a realistic model of the detector and interconnecting kapton microcable as well as realistic models of decoupling capacitors, wire-bonds and on-chip power distribution network are included.

Time-over-threshold processing implementation for silicon detectors with large capacitances

Modern High Energy Physics experiments require more functionality from the multichannel readout circuits which in conjunction with strict limits on power consumption, area occupation and low noise performance set new requirements in the analog front-end electronics design. We discuss the applicability issues and design challenges of a constant-current discharge time-over-threshold (ToT) processing chain for readout of the large capacitance silicon strip detectors. The conclusions are based on measurement results of two prototype ASICs: TOTOl, TOT02. The revealed non-idealities and issues have been identified and are briefly presented in this paper. Moreover, an idea for charge amplifiaction, measurement and timestamping is proposed as a possible remedy for presented matters. This conception uses two cascaded amplifiers and exploits advantages of two different feedback circuits to eliminate the negative impact of a large detector capacitance on the performance of ToT processing while keeping the power consumption at low level.

Optimization of the microcable and detector parameters towards low noise in the STS readout system

Successful operation of the Silicon Tracking System requires charge measurement of each hit with equivalent noise charge lower than 1000 e- rms. Detector channels will not be identical, they will be constructed accordingly to the estimated occupancy, therefore for the readout electronics, detector system will exhibit various parameters. This paper presents the simulation-based study on the required microcable (trace width, dielectric material), detector (aluminum strip resistance) and external passives’ (decoupling capacitors) parameters in the Silicon Tracking System. Studies will be performed using a front-end electronics (charge sensitive amplifier with shaper) designed for the power budget of 10 mA/channel.