Alexander Kotov

Floating-Gate Corner-Enhanced Poly-to-Poly Tunneling in Split-Gate Flash Memory Cells

The poly-to-poly tunneling characteristics in the third-generation SuperFlash memory cell have been analyzed. It has been demonstrated that, even without a sharp floating-gate (FG) tip, the cell still demonstrates the main features of the erase process from previous SuperFlash generations, namely, corner (tip)-enhanced tunneling, asymmetry of the tunneling voltage in forward and reverse directions, strong localization of the tunneling process, and effective suppression of anode hole injection. Furthermore, a new method for measuring the tunneling voltage on a regular FG cell is described. The reliability aspects of corner-enhanced tunneling in the SuperFlash cell are also discussed.

Endurance Characteristics of SuperFlash® Memory

Program/erase endurance characteristics of split-gate SuperFlashreg memory cells are discussed. Various factors which affect memory endurance, including cycling data pattern, cycling frequency, temperature, erase retries, and technology scaling, are investigated. Superior data retention after endurance cycling is demonstrated

Detection of Single-Electron Transfer Events and Capacitance Measurements in Submicron Floating-Gate Memory Cells

A simple technique for monitoring floating gate (FG) charge gain/loss with elementary charge accuracy is proposed. The technique does not require nanoscale FG or low temperature and can be applied to virtually any submicron FG memory cell. The potential applications include precise capacitance measurements, as well as analysis of program, erase, disturb and data retention characteristics of FG memory cells in extremely low range of FG current (down to 10-23A and below)

Generation of single-and double-charge electron traps in tunnel oxide of flash memory cells under Fowler-Nordheim stress

The processes of trap generation and electron trapping in tunnel oxide of SuperFlash® memory cells have been analyzed. It was shown that electrons were mostly trapped by newly generated traps rather than by as-fabricated ones. Due to strongly localized tunneling in SuperFlash cell, it was possible to detect the events of the generation of individual oxide traps. The direct electrical evidence of both single- and double-charge electron trap generation has been observed.

Charge-gain program disturb mechanism in split-gate flash memory cell

Intrinsic charge-gain program disturb mechanism in split-gate flash memory cells has been identified based on simulation results and experimental data obtained on memory arrays fabricated with 0.18 mum SuperFlashreg technology. It was shown that program disturb has the same nature under all three program disturb conditions existing in NOR flash memory array, and is a result of band-to-band tunneling caused by high electric field in the split-gate channel area and subsequent hot electron injection. We also analyzed reliability aspects of this program disturb mechanism on 16-Mbit memory arrays, and found no substantial effect of 10 program-erase cycles on disturb characteristics. The understanding of intrinsic program disturb mechanism is important for split-gate cell technology scaling as well as for optimization of cell design and operating conditions.

Program Disturb Induced by Interface-Trap-Assisted Field and Thermal Electron Emission in the Channel of Split-Gate Memory Cell

A systematic study of program-disturb mechanisms in split-gate memory in the temperature range -45 °C to 150 °C is presented. At low temperatures, the dominant program disturb is initiated by interface-trap-assisted band-to-band tunneling in the split-gate channel area, whereas at high temperatures, it is initiated by surface generation in the select-gate channel area. The effects of single interface traps on program disturb have been analyzed and quantified. A split-gate memory cell with a highquality Si-SiO2 interface provides the strong program-disturb immunity required for high-temperature and automotive embedded applications.

A new method for analysis of cycling-induced degradation components in split-gate flash memory cells

A new simple and fast method for separation of cycling-induced degradation components in split-gate SuperFlash® cell is proposed. The method is based on the effect of tunneling current stabilization during linearly ramped erase voltage.

Small-Size Complex Microwave Devices (CMD) for Onboard Applications

Small-size complex microwave devices (CMD) are designed for applications in onboard air-, sea-, and ground-based radio-electronic systems. They are compact integrated multifunctional devices, which are capable of providing generation, processing, and amplification of complex multifrequency microwave signals, although their operating frequency band is relatively low - about 2%. Small-sized and miniature multiple-beam klystrons are, as a rule, the output power tube of choice for onboard CMDs. CMDs are usually applied to systems where high power, high level of integration (multifunctionality), and high signal quality are desired. Design parameters and performance capability for several onboard CMDs are discussed in this paper. In addition, distinctions between onboard CMDs and state-of-the-art onboard microwave power modules are considered

Optimization of programming conditions and endurance enhancement of SuperFlash® memory

A high-efficient endurance enhancement method for the 3rd-generation SuperFlash® memory has been developed and implemented. It is based on the use of a two-step program operation with reduced programming voltage in the first step (pre-programming). Weak pre-programming provides the reduction of the peak lateral electric field in the channel at the beginning of program operation, which reduces gate oxide degradation in the hot electron injection area. Additional improvement of endurance and memory operating performance can be achieved by the reduction of programming time compensated by insignificant increase of programming voltage. Faster programming delivers lower write energy consumption and higher program-disturb immunity. Program/erase cycling with optimized programming conditions demonstrates typical endurance more than 10 million cycles.

A Detailed Analysis of Hot-Electron Programming Efficiency in 40-nm Split-Gate Flash Memory Cells

Using the precisely measured floating gate capacitance, we were able to extract the absolute values of programming efficiency in the 40-nm SuperFlash® memory cells at different voltage and temperature conditions. Due to the split-gate design, the cell shows very fast and efficient programming. It was shown that the peak injection efficiency may reach 10%.