Viktor Markov

Endurance Characteristics of SuperFlash® Memory

Program/erase endurance characteristics of split-gate SuperFlashreg memory cells are discussed. Various factors which affect memory endurance, including cycling data pattern, cycling frequency, temperature, erase retries, and technology scaling, are investigated. Superior data retention after endurance cycling is demonstrated

Charge-gain program disturb mechanism in split-gate flash memory cell

Intrinsic charge-gain program disturb mechanism in split-gate flash memory cells has been identified based on simulation results and experimental data obtained on memory arrays fabricated with 0.18 mum SuperFlashreg technology. It was shown that program disturb has the same nature under all three program disturb conditions existing in NOR flash memory array, and is a result of band-to-band tunneling caused by high electric field in the split-gate channel area and subsequent hot electron injection. We also analyzed reliability aspects of this program disturb mechanism on 16-Mbit memory arrays, and found no substantial effect of 10 program-erase cycles on disturb characteristics. The understanding of intrinsic program disturb mechanism is important for split-gate cell technology scaling as well as for optimization of cell design and operating conditions.

Program Disturb Induced by Interface-Trap-Assisted Field and Thermal Electron Emission in the Channel of Split-Gate Memory Cell

A systematic study of program-disturb mechanisms in split-gate memory in the temperature range -45 °C to 150 °C is presented. At low temperatures, the dominant program disturb is initiated by interface-trap-assisted band-to-band tunneling in the split-gate channel area, whereas at high temperatures, it is initiated by surface generation in the select-gate channel area. The effects of single interface traps on program disturb have been analyzed and quantified. A split-gate memory cell with a highquality Si-SiO2 interface provides the strong program-disturb immunity required for high-temperature and automotive embedded applications.

Optimization of programming conditions and endurance enhancement of SuperFlash® memory

A high-efficient endurance enhancement method for the 3rd-generation SuperFlash® memory has been developed and implemented. It is based on the use of a two-step program operation with reduced programming voltage in the first step (pre-programming). Weak pre-programming provides the reduction of the peak lateral electric field in the channel at the beginning of program operation, which reduces gate oxide degradation in the hot electron injection area. Additional improvement of endurance and memory operating performance can be achieved by the reduction of programming time compensated by insignificant increase of programming voltage. Faster programming delivers lower write energy consumption and higher program-disturb immunity. Program/erase cycling with optimized programming conditions demonstrates typical endurance more than 10 million cycles.

40nm Embedded Self-Aligned Split-Gate Flash Technology for High-Density Automotive Microcontrollers

This paper successfully demonstrates a logic- compatible, high performance and high reliability, automotive-grade 2.5V embedded NVM process extending over several generations. A high-density flash macro is used to debug process complexities which arise from the add-on modules. The modular approach is adopted for integrating self-aligned, floating-gate-based split-gate SuperFlash® ESF3 cell into 40nm CMOS logic process. Key features of the product-like Macro are dual power supply with input voltage fluctuations, wide operating temperature range from -40ºC to 150ºC, fast byte/word program under 10s and sector/chip erase under 10ms. The macro random read access time is only 8ns under worst case conditions. Key process monitors are characterization and yield of the Macro. Endurance was extended to 200k cycles and satisfy automotive grade requirement with wide read margin. Post-cycling data retention performs very well up to 150ºC. Wafer sort yield is in high double digits, with consistent wafer-to-wafer and within-wafer uniformity, showing good process control. The technology is suitable for high-speed automotive MCU, as well as IoT, smart card, and industrial MCU applications.

SuperFlash® Scaling Aspects: Program Disturb

A systematic study of dominant program-disturb mechanisms in advanced embedded split-gate SuperFlash memory across ambient temperature ranging from -45°C to 175°C is presented. At low temperatures program disturb is initiated by trap-assisted band-to-band tunneling in the split-gate channel area and/or trap-assisted tunneling via thin select gate oxide and at high temperatures - by surface generation in select-gate channel. Effects of single traps on program disturb in split-gate memory have been analyzed. Good quality of thin select gate oxide and its interface with channel is important to meet stringent requirements of the wide-temperature embedded memory applications.