Yuri Tkachev

Floating-Gate Corner-Enhanced Poly-to-Poly Tunneling in Split-Gate Flash Memory Cells

The poly-to-poly tunneling characteristics in the third-generation SuperFlash memory cell have been analyzed. It has been demonstrated that, even without a sharp floating-gate (FG) tip, the cell still demonstrates the main features of the erase process from previous SuperFlash generations, namely, corner (tip)-enhanced tunneling, asymmetry of the tunneling voltage in forward and reverse directions, strong localization of the tunneling process, and effective suppression of anode hole injection. Furthermore, a new method for measuring the tunneling voltage on a regular FG cell is described. The reliability aspects of corner-enhanced tunneling in the SuperFlash cell are also discussed.

Detection of Single-Electron Transfer Events and Capacitance Measurements in Submicron Floating-Gate Memory Cells

A simple technique for monitoring floating gate (FG) charge gain/loss with elementary charge accuracy is proposed. The technique does not require nanoscale FG or low temperature and can be applied to virtually any submicron FG memory cell. The potential applications include precise capacitance measurements, as well as analysis of program, erase, disturb and data retention characteristics of FG memory cells in extremely low range of FG current (down to 10-23A and below)

Generation of single-and double-charge electron traps in tunnel oxide of flash memory cells under Fowler-Nordheim stress

The processes of trap generation and electron trapping in tunnel oxide of SuperFlash® memory cells have been analyzed. It was shown that electrons were mostly trapped by newly generated traps rather than by as-fabricated ones. Due to strongly localized tunneling in SuperFlash cell, it was possible to detect the events of the generation of individual oxide traps. The direct electrical evidence of both single- and double-charge electron trap generation has been observed.

A new method for analysis of cycling-induced degradation components in split-gate flash memory cells

A new simple and fast method for separation of cycling-induced degradation components in split-gate SuperFlash® cell is proposed. The method is based on the effect of tunneling current stabilization during linearly ramped erase voltage.

Extraction of floating-gate capacitive parameters in split-gate flash memory cells

A new fast and simple method for extraction of capacitive coupling coefficients in a split-gate flash memory cell is described. The method is based on the modulation of cells erase characteristics by the bias applied to the gates during read and erase operations. The absolute values of the capacitance between the floating gate and other nodes are also extracted using the effect of modulation of cell conductance caused by the transfer of individual electrons to/from the floating gate.

Common-floating gate test structure for separation of cycling-induced degradation components in split-gate flash memory cells

The program-erase cycling-induced degradation mechanisms in a split-gate SuperFlash® memory cell were analyzed using a test structure containing two cells with a common floating gate. This test structure allowed us to separate the degradation mechanisms taking place in the floating-gate oxide and tunnel oxide during cycling. It was demonstrated that the program-induced floating gate oxide degradation becomes less significant for the advanced SuperFlash technology, which uses lower programming voltage.

A differential method for analysis of hot-electron degradation in floating-gate memory cells with a single-trap resolution

A new differential method for the precise analysis of hot-electron degradation in the floating-gate memory cells with a single-trap resolution is described. The method is based on the use of a test structure, containing two cells with a shared floating gate.

Field-induced generation of electron traps in the tunnel oxide of flash memory cells

The processes of trap generation and electron trapping in the tunnel oxide of SuperFlash memory cells have been analyzed. The strongly non-uniform distribution of electric field in the SuperFlash cell allowed us to rule out the electron- or hole-related mechanisms of trap generation. The experimental results of single-trap-induced modulation of the tunneling rate, and the analysis of field and potential distribution in the tunnel oxide, point to the high electric field as a direct cause of electron-trap generation.

A Detailed Analysis of Hot-Electron Programming Efficiency in 40-nm Split-Gate Flash Memory Cells

Using the precisely measured floating gate capacitance, we were able to extract the absolute values of programming efficiency in the 40-nm SuperFlash® memory cells at different voltage and temperature conditions. Due to the split-gate design, the cell shows very fast and efficient programming. It was shown that the peak injection efficiency may reach 10%.

The sources of erase voltage variability in split-gate flash memory cell arrays

We performed a comprehensive analysis of the voltage-to-erase (Verase) distribution in split-gate flash memory cell arrays. It was shown that Verase distribution is mostly determined by the tunneling voltage variations. Other factors, such as distributions of coupling ratio and FG channel parameters, have a minor effect on Verase variability.