Amitay Levi

A novel 3 volts-only, small sector erase, high density flash E/sup 2/PROM

A split gate Flash E/sup 2/PROM memory cell with Fowler-Nordhiem tunneling erase, and high efficiency hot electron programming is presented. Gate current measurements show that one out of every 300 channel electrons is injected into the gate under worst case programming conditions. The greater efficiency of cell allows the use of small on-chip multipliers for single 3v Vcc operation. High cell reliability is achieved through low floating gate oxide field (oxide reliability) and small programming current (contact reliability). It is shown that the cell is immune to read and write disturb conditions.<<ETX>>

Endurance Characteristics of SuperFlash® Memory

Program/erase endurance characteristics of split-gate SuperFlashreg memory cells are discussed. Various factors which affect memory endurance, including cycling data pattern, cycling frequency, temperature, erase retries, and technology scaling, are investigated. Superior data retention after endurance cycling is demonstrated

Charge-gain program disturb mechanism in split-gate flash memory cell

Intrinsic charge-gain program disturb mechanism in split-gate flash memory cells has been identified based on simulation results and experimental data obtained on memory arrays fabricated with 0.18 mum SuperFlashreg technology. It was shown that program disturb has the same nature under all three program disturb conditions existing in NOR flash memory array, and is a result of band-to-band tunneling caused by high electric field in the split-gate channel area and subsequent hot electron injection. We also analyzed reliability aspects of this program disturb mechanism on 16-Mbit memory arrays, and found no substantial effect of 10 program-erase cycles on disturb characteristics. The understanding of intrinsic program disturb mechanism is important for split-gate cell technology scaling as well as for optimization of cell design and operating conditions.