Mario M. Pelella

Low-voltage transient bipolar effect induced by dynamic floating-body charging in scaled PD/SOI MOSFETs

An increased significance of the parasitic bipolar transistor (BJT) in scaled floating-body partially depleted SOI MOSFETs under transient conditions is described. The transient parasitic BJT effect is analyzed using both simulations and high-speed pulse measurements of pass transistors in a sub-0.25 /spl mu/m SOI technology. The transient BJT current can be significant even at low drain-source voltages, well below the device breakdown voltage, and does not scale with technology. Our analysis shows that it can be problematic in digital circuit operation, possibly causing write disturbs in SRAMs and decreased retention times for DRAMs. Proper device/circuit design, suggested by our analysis, can however control the problems.

Floating-body effects in partially depleted SOI CMOS circuits

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.

Physical modeling of temperature dependences of SOI CMOS devices and circuits including self-heating

To simulate and examine temperature and self-heating effects in Silicon-On-Insulator (SOI) devices and circuits, a physical temperature-dependence model is implemented into the SOISPICE fully depleted (FD) and nonfully depleted (NFD) SOI MOSFET models. Due to the physical nature of the device models, the temperature-dependence modeling, which enables a device self-heating option as well, is straightforward and requires no new parameters. The modeling is verified by DC and transient measurements of scaled test devices, and in the process physical insight on floating-body effects in temperature is attained. The utility of the modeling is exemplified with a study of the temperature and self-heating effects in an SOI CMOS NAND ring oscillator. SOISPICE transient simulations of the circuit, with floating and tied bodies, reveal how speed and power depend on ambient temperature, and they predict no significant dynamic self-heating, irrespective of the ambient temperature.

Scalable PD/SOI CMOS with floating bodies

An insightful analysis of the floating-body (FB) effect on off-state current (I/sub off/) in PD/SOI MOSFETs is done based on simulations calibrated to a published scaled SOI CMOS technology (Chau et al., 1997). In contrast to the conclusion drawn by Chau, the simulations reveal that proven, easily integrated processes for enhancing carrier recombination in the source/drain junction region, in conjunction with the normal elevated chip temperature of operation, can effectively suppress the FB-induced increase of I/sub off/, thus enabling exploitation of the unique benefits of scaled PD/SOI CMOS circuits.

Hysteresis in floating-body PD/SOI CMOS circuits

In this paper the hysteretic (history-dependent) propagation gate delay of floating-body (FB) partially depleted (PD) SOI CMOS circuits is investigated. The change in gate propagation delay with time is examined with no preconditioning of the floating-body. The simulation-based analysis includes the sensitivity of the hysteresis to supply voltage, Wp/Wn (beta ratio), duty cycle, slew rate, output load, and initial state of the circuit. Basic physical mechanisms underlying the hysteretic circuit behavior are examined. The results identify the main contributors and general trends of hysteresis in FB PD/SOI circuits. The insight gained can ultimately be incorporated into conventional circuit timing tools. The results also reveal a circuit sizing methodology to minimize the hysteresis effects in circuits using PD/SOI technology.

Control of off-state current in scaled PD/SOI CMOS digital circuits

A recent study of the scalability of partially depleted (PD) SOI CMOS technology (Chau et al. IEEE IEDM Tech. Dig., p. 591, Dec. 1997) led to the conclusion that it was no better than bulk-Si CMOS for sub-0.25 /spl mu/m digital applications, irrespective of its inherent advantages, because of the higher threshold voltage (V/sub T/) needed to limit the off-state current (I/sub off/) of the nMOSFET, which tends to be high because of the drain (V/sub DS/)-induced floating-body (FB) effect (i.e. the kink effect) in addition to the barrier lowering (DIBL). In this paper, we give a physically insightful analysis of the FB effect on I/sub off/ based on the scaled PD/SOI CMOS technology described by Chau et al. which contradicts the negative assessment of the scalability of SOI digital ICs. Device and circuit simulations of operation at high chip temperatures (55-85/spl deg/C) that are typical for high-performance circuits show that the FB effect can be naturally ameliorated, and that previously proven techniques for controlling FB effects are also effective in limiting I/sub off/. Furthermore, we show that the temperature coefficient of the body-source voltage (V/sub BS/) is strongly dependent on the recombination current (I/sub R/) of the junctions, and the impact on circuit performance of an increased I/sub R/ is shown to be negligible.

Low-voltage transient bipolar effect induced by dynamic floating-body charging in PD/SOI MOSFETs

Partially-depleted (PD) SOI MOSFETs offer improved threshold control and sensitivity over fully depleted devices, but the effects of dynamic floating-body charging on the threshold voltage VT(t) can possibly lead to instabilities in PD/SOI circuits. We show in this paper that the dynamic charging of the body can also induce a parasitic bipolar-transistor (BJT) transient current which can be significant even at low voltages well below the drain-source breakdown defined by the BJT. Our results indicate that if device/circuit design allows substantial variation of the body charge, then the transient BJT current could be large enough to upset the logic or memory (SRAM or DRAM) function of a chip. They further show that such an upset becomes more probable as the device is scaled, and they give insight regarding device and circuit design to reduce the probability.

SOI floating-body, device and circuit issues

This paper focuses on floating-body effects in MOSFETs and circuits on SOI substrates. We review different ways to coexist with these effects and particularly how to take advantage from them. It is shown that there is no blanket solution, but more a palette of approaches. Choosing the most appropriate one to a given application is addressed.

Design and Characterization of ESD Protection Devices for High-Speed I/O in Advanced SOI Technology

This paper focuses on the characterization, modeling, and design of electrostatic discharge (ESD) protection devices such as the gated diode, the bulk substrate diode, and the double-well field-effect diode (DWFED) in 45 nm silicon-on-insulator technology. ESD protection capabilities are investigated using very fast transmission line pulsing tests to predict a devices performance in charged device model (CDM) ESD events. Device capacitance, which is critical for high-speed input/output performance, is evaluated, and biasing schemes and processing techniques are proposed to reduce the parasitic capacitance during normal operating conditions. Technology computer-aided design simulations are used to interpret the physical effects. The implementation of devices for meeting CDM protection requirements is discussed. Evaluation results identify DWFED as a promising candidate for the pad-based local-clamping scheme.

BiMOS modeling for reliable SOI circuit design

Summary form only given. Recent work has clearly revealed that transient current in the parasitic bipolar junction transistor (BJT) of the floating-body SOI MOSFET can be significant and degrading even in SOI circuits operating at voltages well below the BJT-defined drain-source breakdown. The BJT is also critically important with regard to soft errors in low-voltage SOI memory circuits. In these cases, the BJT current is driven by dynamic charging of the body and concomitant forward biasing of the source (or drain) junction, supported by capacitive, or charge coupling between the BJT and the MOSFET. A reliable circuit model for the floating-body SOI MOSFET must therefore account for the coupled BJT. In this paper we present a new, quasi-2D parasitic BJT model physically coupled to the SOISPICE MOSFET models and defined in terms of their parameters. We further use physical insight derived from this BiMOS modeling to identify a new means of controlling the transient BJT, or leakage current in SOI MOSFETs which could be exploited in design.