Ali Soltani Tehrani

A Comparative Analysis of the Complexity/Accuracy Tradeoff in Power Amplifier Behavioral Models

A comparative study of state-of-the-art behavioral models for microwave power amplifiers (PAs) is presented in this paper. After establishing a proper definition for accuracy and complexity for PA behavioral models, a short description on various behavioral models is presented. The main focus of this paper is on the modeling accuracy as a function of computational complexity. Data is collected from measurements on two PAs-a general-purpose amplifier and a Doherty PA designed for WiMAX-for different output power levels. The models are characterized in terms of accuracy and complexity for both in-band and out-of-band error. The results show that, among the models studied, the generalized memory polynomial behavioral model has the best tradeoff for accuracy versus complexity for both PAs, and can obtain high performance at half of the computational cost of all other models analyzed.

Linearization of Efficiency-Optimized Dynamic Load Modulation Transmitter Architectures

In this paper, a detailed linearization procedure for dynamic load modulation (DLM) transmitter architectures is proposed for the first time. Compared with the conventional single-input/single-output digital predistortion (DPD) approach used with traditional power amplifiers (PAs), the proposed linearization scheme is based on a regular memory DPD in combination with an efficiency-optimized static one-to-two mapping inverse model, which constructs the predistorted input signals to the DLM transmitter. The time-alignment issue, which is very important to this dual-input architecture, is also considered. The proposed technique is demonstrated by a 1-GHz 10-W LDMOS PA that employs a varactor-based tunable matching network. A normalized mean square error of -35 dB, and adjacent channel leakage ratio of -43 dBc is achieved, with an average power-added efficiency of 53% for a single-carrier WCDMA signal with 7-dB peak-to-average ratio. Finally, it is shown that the time-alignment sensitivity is relaxed when the proposed linearization scheme is used. This means that the overall complexity of the transmitter implementation can be reduced.

Digital Predistortion for High Efficiency Power Amplifier Architectures Using a Dual-Input Modeling Approach

In this paper, a novel model is proposed for dual-input high efficiency power amplifier (PA) architectures, such as envelope tracking (ET) and varactor-based dynamic load modulation (DLM). Compared to the traditional single-input modeling approach, the proposed model incorporates the baseband supply voltage/load control as an input. This advantage makes the new approach capable to achieve maximized average power-added efficiency (PAE) and minimized output distortion simultaneously. Furthermore, the new approach has shown to be robust towards time misalignment between the RF input and baseband supply voltage/load control signals, and it can be applied with a reduced-bandwidth baseband supply voltage/load control. Experiments have been performed in a varactor-based DLM PA architecture to evaluate the new modeling approach. The results show that it can achieve 9 and 7 dB better performance than the traditional approaches in terms of adjacent channel leakage ratio and normalized mean square error, respectively. At the same time, the average PAE is maximized. Similar results have been achieved with the proposed model even when reduced-bandwidth baseband load control signal is used or time misalignment between the RF and baseband load control input signals exists. Although the new approach is only tested with DLM architecture in this paper, it is very general and can be applied to ET architectures as well.

Modeling of long term memory effects in RF power amplifiers with dynamic parameters

This paper presents a new radio frequency power amplifier behavioral model that is capable of modeling long term memory effects. The proposed model is derived by assuming linear dependence of the parameters of a conventional model to a long term memory parameter, which enables the model to better track the signal-induced changes of the power amplifier electrical behavior. The model is experimentally tested on a 100W Doherty power amplifier, with a signal that has a step-like change in power, representative of a realistic communication system with bursty behavior. Results show that the proposed model is able to improve the normalized mean squared error performance by around 2–3 dB.

Dynamic load modulation of high power amplifiers with varactor-based matching networks

In this paper, the results of dynamic load modulation on a high power amplifier is shown with experiments. A simple static nonlinear model is used as an inverse model, and by dynamically controlling both the input signal to the power amplifier and the load impedance, high efficiency operation of the power amplifier is achieved. The modulated measurements show the feasibility of dynamic load modulation for practical high power, high frequency applications.

Time alignment in a dynamic load modulation transmitter architecture

A time alignment algorithm is proposed for a dynamic load modulation transmitter architecture. The effect of time mismatch between the RF input and baseband control signal is investigated by experiments, and it is shown that unsynchronized signals can result in severe distortion of the output signal. In this paper, cross correlation and sinc interpolation techniques are applied to estimate and compensate for the sub-sample delay between the RF signal path and the baseband control signal path in the measurement system. The performance of the dynamic load modulation transmitter architecture with accurate time alignment is shown by experimental results. The measurement shows that, the efficiency is greatly affected by time alignment and the spectral regrowth is suppressed by more than 10 dB.

Comparison of bandwidth reduction schemes in dynamic load modulation power amplifier architectures

This paper compares bandwidth reduction schemes for baseband control signals used in high efficiency power amplifier (PA) architectures, such as envelope tracking and dynamic load modulation (DLM). The baseband control signal used in such architectures usually has 3–4 times wider bandwidth than the modulated radio frequency (RF) signal. Such a wideband signal brings challenges for practical hardware design. In this paper, two bandwidth reduction schemes originally used in envelope tracking are applied on a DLM PA. The performance of both schemes are investigated by simulation. The results show that the bandwidth of the baseband control signal can be effectively reduced from 12.5 MHz to 4 MHz, while at the same time, maintaining a 49% average power-added and acceptable linearity.

Compensation of transmitter distortion using a nonlinear modeling approach

In this paper, a nonlinear modeling approach is used to demonstrate a joint compensation scheme for the linear and nonlinear distortions in the I/Q modulator and the power amplifier. Based on this nonlinear model, a digital pre-compensator is constructed. The effects of these two most dominant nonlinear components in a modern transmitter can therefore be digitally pre-compensated in a single step. The results are verified by experiments, and the proposed approach shows promising performance.

Dual-input nonlinear modeling for I/Q modulator distortion compensation

This paper focuses on modeling and compensation of both linear and nonlinear distortions in RF I/Q modulators using a dual-input Volterra series-based modeling approach. Moreover, dual-input memory polynomial and dual-input dynamic deviation reduction-based Volterra series models are proposed. The proposed models are evaluated by digital pre-compensation of a high performance I/Q modulator with a wideband input signal. The results show that the proposed dual-input models efficiently compensate for distortion in the I/Q modulator and may therefore greatly improve performance in modern communication systems.

Complexity analysis of power amplifier behavioral models

In this paper efficient computer implementations of some of the most commonly used Volterra series based power amplifier behavioral models are proposed. The desired efficiency is in regard to algorithm complexity and floating point operations. Finally a comparative overview of the different behavioral models with respect to their complexity is presented.